diff --git a/src/main/scala/backBoard/Dout16.scala b/src/main/scala/backBoard/Dout16.scala
index 932879d..bd5aff9 100644
--- a/src/main/scala/backBoard/Dout16.scala
+++ b/src/main/scala/backBoard/Dout16.scala
@@ -24,6 +24,7 @@ with BackBoardSlvStatusPR
 with BackBoardSlvOut16{
   val out = IO(Output(UInt(16.W)))
   val flt = IO(Input(Vec(2, Bool())))
+  val v24Det = IO(Input(Bool()))
   val outReg  = RegInit(0.U(16.W))
 
   when( isCrcPass & downRegTemp(0)(3,0) === 0.U ){
@@ -40,6 +41,7 @@ with BackBoardSlvOut16{
     upReg(2) := outReg(7,0)
     upReg(3) := outReg(15,8)
     upReg(4) := Cat( ~flt(1), ~flt(0) )
+    upReg(5) := Cat( ~v24Det, 0.U(7.W) )
   }
 
   when( statusPage === 1.U ){
diff --git a/src/main/scala/backBoard/Qei.scala b/src/main/scala/backBoard/Qei.scala.bk
similarity index 100%
rename from src/main/scala/backBoard/Qei.scala
rename to src/main/scala/backBoard/Qei.scala.bk
diff --git a/src/main/scala/backBoard/SpiSlv.scala b/src/main/scala/backBoard/SpiSlv.scala.bk
similarity index 100%
rename from src/main/scala/backBoard/SpiSlv.scala
rename to src/main/scala/backBoard/SpiSlv.scala.bk
diff --git a/src/main/scala/backBoard/ebus/BackBoardMst.scala b/src/main/scala/backBoard/ebus/BackBoardMst.scala.bk
similarity index 100%
rename from src/main/scala/backBoard/ebus/BackBoardMst.scala
rename to src/main/scala/backBoard/ebus/BackBoardMst.scala.bk
diff --git a/src/main/scala/backBoard/ebus/BackBoardSlv.scala b/src/main/scala/backBoard/ebus/BackBoardSlv.scala.bk
similarity index 100%
rename from src/main/scala/backBoard/ebus/BackBoardSlv.scala
rename to src/main/scala/backBoard/ebus/BackBoardSlv.scala.bk
diff --git a/src/main/scala/backBoard/ebus/CDR4MultiIn.scala b/src/main/scala/backBoard/ebus/CDR4MultiIn.scala.bk
similarity index 100%
rename from src/main/scala/backBoard/ebus/CDR4MultiIn.scala
rename to src/main/scala/backBoard/ebus/CDR4MultiIn.scala.bk
diff --git a/src/main/scala/backBoard/ebus/CDROutBus.scala b/src/main/scala/backBoard/ebus/CDROutBus.scala.bk
similarity index 100%
rename from src/main/scala/backBoard/ebus/CDROutBus.scala
rename to src/main/scala/backBoard/ebus/CDROutBus.scala.bk
diff --git a/src/main/scala/backBoard/ebus/FSMC.scala b/src/main/scala/backBoard/ebus/FSMC.scala.bk
similarity index 100%
rename from src/main/scala/backBoard/ebus/FSMC.scala
rename to src/main/scala/backBoard/ebus/FSMC.scala.bk
diff --git a/src/main/scala/backBoard/ebus/SpiSlv.scala b/src/main/scala/backBoard/ebus/SpiSlv.scala.bk
similarity index 100%
rename from src/main/scala/backBoard/ebus/SpiSlv.scala
rename to src/main/scala/backBoard/ebus/SpiSlv.scala.bk
diff --git a/src/main/verilog/do16_top.v b/src/main/verilog/do16_top.v
index 24e1269..aa06293 100644
--- a/src/main/verilog/do16_top.v
+++ b/src/main/verilog/do16_top.v
@@ -22,7 +22,8 @@ module do16_top(
   output        LED_PR,
   output [15:0] out,
   input         flt_0,
-  input         flt_1
+  input         flt_1,
+  input         v24Det
 
 );
 
@@ -297,6 +298,7 @@ DOut16 i_dout16(
   .out(out),
   .flt_0(flt_0),
   .flt_1(flt_1),
+  .v24Det(v24Det),
 
   .io_lvdsSlv_downstream_rx_data_out(downstream_rx_data_out),
   .io_lvdsSlv_downstream_rx_data_valid(downstream_rx_data_valid),