ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

dout增加公共端IO

Browse Source
This commit is contained in:
RuigeLee
2024-06-14 19:00:41 +08:00
parent 715a1e6c08
commit 7aa7ea7ec6
10 changed files with 5 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

35
src/main/scala/backBoard/SpiSlv.scala
View File

@@ -1,35 +0,0 @@
package BACK
import chisel3._
import chisel3.util._
trait BackBoardSpiSlv{ this: BackBoardSlvLocal =>
val sck = Wire(Bool())
val mosi = Wire(Bool())
val csn = Wire(Bool())
val clk100M = Wire(Bool())
val shiftSCK = withClockAndReset( clk100M.asClock, reset ){ ShiftRegisters(sck, 3, false.B, true.B) }
val shiftCSn = withClockAndReset( clk100M.asClock, reset ){ ShiftRegisters(csn, 3, true.B, true.B) }
val shiftMOSI = withClockAndReset( clk100M.asClock, reset ){ ShiftRegisters(mosi, 3) }
val isSckPosedge = ~shiftSCK(2) & shiftSCK(1)
val isSckNegedge = shiftSCK(2) & ~shiftSCK(1)
val downReg_100M = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(8*8.W)) }
val upReg_100M = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(8*8.W)) }
val misoReg = withClockAndReset( clk100M.asClock, reset ){ Reg(Bool()) }
withClockAndReset( clk100M.asClock, reset ){//100M
when( isSckPosedge & shiftCSn(2) ){
misoReg := downReg_100M.extract(0)
downReg_100M := downReg_100M >> 1
upReg_100M := Cat( upReg_100M(8*8-1,1), shiftMOSI(2) )
}
}
}