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dout增加公共端IO

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RuigeLee
2024-06-14 19:00:41 +08:00
parent 715a1e6c08
commit 7aa7ea7ec6
10 changed files with 5 additions and 1 deletions
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49
src/main/scala/backBoard/Qei.scala
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@@ -1,49 +0,0 @@
package BACK
import chisel3._
import chisel3.util._
trait BackBoardSlvQei{ this: BackBoardSlvLocal =>
val phaseA = Wire(Bool())
val phaseB = Wire(Bool())
val counter = Reg(UInt(32.W))
val encordNxt = Cat( phaseB, phaseA )
val encordCur = RegNext(encordNxt)
val isCheckDirect = Wire(Bool())
val is2Multi = Wire(Bool())
val is4Multi = Wire(Bool())
val isAdvA =
( encordCur === "b00".U & encordNxt === "b01".U ) |
( encordCur === "b01".U & encordNxt === "b11".U ) |
( encordCur === "b11".U & encordNxt === "b10".U ) |
( encordCur === "b10".U & encordNxt === "b00".U )
val isAdvB =
( encordNxt === "b00".U & encordCur === "b01".U ) |
( encordNxt === "b01".U & encordCur === "b11".U ) |
( encordNxt === "b11".U & encordCur === "b10".U ) |
( encordNxt === "b10".U & encordCur === "b00".U )
val isMiss = encordCur === ~encordNxt
val isKeep = encordCur === encordNxt
when(){
when( isMiss ){
printf("Warning! QEI Miss one pulse!\n")
} .elsewhen( isAdvA ){
} .elsewhen( isAdvB ){
} .otherwise{
assert( isKeep )
}
}
}