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ready to test tilelink slv

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RuigeLee
2023-07-04 23:36:34 +08:00
parent 5bd8b261bf
commit 78a2f4ba47
1 changed files with 1 additions and 1 deletions
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2
src/main/scala/mac/MacTilelink.scala
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@@ -1164,7 +1164,7 @@ val masterStage = Cat(MasterWbTX, MasterWbRX, (ReadTxDataFromMemory & ~BlockRead
io.tlSlv.get.A.ready := RegNext(io.RegCs.orR, false.B) | BDAck
io.tlSlv.get.A.ready := RegNext(io.RegCs.orR & ~io.tlSlv.get.A.fire, false.B) | BDAck
assert( ~(io.tlSlv.get.A.ready & ~io.tlSlv.get.A.valid) )
when( io.tlSlv.get.A.fire & (~(io.tlSlv.get.A.bits.mask.orR) | CsMiss) ){