From 78a2f4ba47fa14a793eb21243e98a8cd6f1dd9df Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Tue, 4 Jul 2023 23:36:34 +0800 Subject: [PATCH] ready to test tilelink slv --- src/main/scala/mac/MacTilelink.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/mac/MacTilelink.scala b/src/main/scala/mac/MacTilelink.scala index e6d9e45..536b783 100644 --- a/src/main/scala/mac/MacTilelink.scala +++ b/src/main/scala/mac/MacTilelink.scala @@ -1164,7 +1164,7 @@ val masterStage = Cat(MasterWbTX, MasterWbRX, (ReadTxDataFromMemory & ~BlockRead - io.tlSlv.get.A.ready := RegNext(io.RegCs.orR, false.B) | BDAck + io.tlSlv.get.A.ready := RegNext(io.RegCs.orR & ~io.tlSlv.get.A.fire, false.B) | BDAck assert( ~(io.tlSlv.get.A.ready & ~io.tlSlv.get.A.valid) ) when( io.tlSlv.get.A.fire & (~(io.tlSlv.get.A.bits.mask.orR) | CsMiss) ){