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上传FPGA配置文件

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Ruige Lee
2025-05-23 10:44:23 +08:00
parent 4b5f45e342
commit 77a037a17e
2 changed files with 225 additions and 0 deletions
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189
src/main/resources/FPGATop.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2025/05/13 11:43:33
// Design Name:
// Module Name: FPGATop
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FPGATop(
input clkin,
input resetIn,
input dDatIn_p,
input dDatIn_n,
output dDatOut_p,
output dDatOut_n,
input uDatIn_p,
input uDatIn_n,
output uDatOut_p,
output uDatOut_n,
input sck,
input mosi,
output miso,
input csn,
input io_iqspi_sck,
inout [3:0] io_iqspi_data,
input io_iqspi_csn,
output interrupt,
output [3:0] io_led
);
wire clk50M;
wire clk400M;
wire reset;
wire dDatIn;
wire dDatOut;
wire uDatIn;
wire uDatOut;
clk_wiz_0 i_clk
(
// Clock out ports
.clk_out1(clk50M),
.clk_out2(clk400M),
// Clock in ports
.clk_in1(clkin)
);
// proc_sys_reset_0 i_proc_sys_reset(
// .slowest_sync_clk(clk50M),
// .ext_reset_in(resetIn),
// .aux_reset_in(1'b0),
// .mb_debug_sys_rst(1'b0),
// .dcm_locked(1'b1),
// .mb_reset(),
// .bus_struct_reset(),
// .peripheral_reset(reset),
// .interconnect_aresetn(),
// .peripheral_aresetn()
// );
assign reset = resetIn;
wire [3:0] iqspi_mosi;
wire [3:0] iqspi_miso;
wire iqspi_isDirIn;
wire isSoftReset;
wire [7:0] led;
ShinTop i_ShinTop(
.clock(clk50M),
.reset(reset),//|isSoftReset),
.io_clk8x(clk400M),
.io_dDatIn(dDatIn),
.io_dDatOut(dDatOut),
.io_uDatIn(uDatIn),
.io_uDatOut(uDatOut),
.io_ospi_sck(sck),
.io_ospi_mosi(mosi),
.io_ospi_miso(miso),
.io_ospi_csn(csn),
.io_rsp_valid(interrupt),
.io_rsp_bits_isError(),
.io_iqspi_sck(io_iqspi_sck),
.io_iqspi_mosi(iqspi_mosi),
.io_iqspi_miso(iqspi_miso),
.io_iqspi_isDirIn(iqspi_isDirIn),
.io_iqspi_csn(io_iqspi_csn),
.io_oqspi_sck(1'b0),
.io_oqspi_mosi(4'b0),
.io_oqspi_miso(),
.io_oqspi_isDirIn(),
.io_oqspi_csn(1'b1),
.io_iSync_0(),
.io_iSync_1(),
.io_iSync_2(),
.io_iSync_3(),
.io_oSync_0(),
.io_oSync_1(),
.io_oSync_2(),
.io_oSync_3(),
.io_isSoftReset(isSoftReset),
.io_ledTest(led)
);
assign io_led = led[5:2];
IOBUF QSPI_D0_inst (
.O(iqspi_mosi[0]), // Buffer output
.IO(io_iqspi_data[0]), // Buffer inout port (connect directly to top-level port)
.I(iqspi_miso[0]), // Buffer input
.T(iqspi_isDirIn) // 3-state enable input, high=input, low=output
);
IOBUF QSPI_D1_inst (
.O(iqspi_mosi[1]), // Buffer output
.IO(io_iqspi_data[1]), // Buffer inout port (connect directly to top-level port)
.I(iqspi_miso[1]), // Buffer input
.T(iqspi_isDirIn) // 3-state enable input, high=input, low=output
);
IOBUF QSPI_D2_inst (
.O(iqspi_mosi[2]), // Buffer output
.IO(io_iqspi_data[2]), // Buffer inout port (connect directly to top-level port)
.I(iqspi_miso[2]), // Buffer input
.T(iqspi_isDirIn) // 3-state enable input, high=input, low=output
);
IOBUF QSPI_D3_inst (
.O(iqspi_mosi[3]), // Buffer output
.IO(io_iqspi_data[3]), // Buffer inout port (connect directly to top-level port)
.I(iqspi_miso[3]), // Buffer input
.T(iqspi_isDirIn) // 3-state enable input, high=input, low=output
);
IBUFDS i_dDatIn (
.O(dDatIn), // Buffer output
.I(dDatIn_p), // Diff_p buffer input (connect directly to top-level port)
.IB(dDatIn_n) // Diff_n buffer input (connect directly to top-level port)
);
IBUFDS i_uDatIn (
.O(uDatIn), // Buffer output
.I(uDatIn_p), // Diff_p buffer input (connect directly to top-level port)
.IB(uDatIn_n) // Diff_n buffer input (connect directly to top-level port)
);
OBUFDS i_dDatOut (
.O(dDatOut_p), // Diff_p output (connect directly to top-level port)
.OB(dDatOut_n), // Diff_n output (connect directly to top-level port)
.I(dDatOut) // Buffer input
);
OBUFDS i_uDatOut (
.O(uDatOut_p), // Diff_p output (connect directly to top-level port)
.OB(uDatOut_n), // Diff_n output (connect directly to top-level port)
.I(uDatOut) // Buffer input
);
endmodule

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src/main/resources/constr.xdc Normal file
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set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS33} [get_ports clkin]
#CPUPC8
set_property -dict {PACKAGE_PIN P1 IOSTANDARD LVCMOS33} [get_ports resetIn]
set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS33} [get_ports mosi]
set_property -dict {PACKAGE_PIN T20 IOSTANDARD LVCMOS33} [get_ports miso]
set_property -dict {PACKAGE_PIN W21 IOSTANDARD LVCMOS33} [get_ports sck]
set_property -dict {PACKAGE_PIN W22 IOSTANDARD LVCMOS33} [get_ports csn]
set_property -dict {PACKAGE_PIN F16 IOSTANDARD TMDS_33} [get_ports dDatOut_p]
set_property -dict {PACKAGE_PIN E16 IOSTANDARD TMDS_33} [get_ports dDatIn_p]
set_property -dict {PACKAGE_PIN E13 IOSTANDARD TMDS_33} [get_ports uDatOut_p]
set_property -dict {PACKAGE_PIN F13 IOSTANDARD TMDS_33} [get_ports uDatIn_p]
#CPU PC7
set_property -dict {PACKAGE_PIN P5 IOSTANDARD LVCMOS33} [get_ports interrupt]
set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS33} [get_ports io_iqspi_sck]
set_property -dict {PACKAGE_PIN T21 IOSTANDARD LVCMOS33} [get_ports io_iqspi_data[0]]
set_property -dict {PACKAGE_PIN U21 IOSTANDARD LVCMOS33} [get_ports io_iqspi_data[1]]
set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVCMOS33} [get_ports io_iqspi_data[2]]
set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS33} [get_ports io_iqspi_data[3]]
set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS33} [get_ports io_iqspi_csn]
set_property -dict {PACKAGE_PIN P2 IOSTANDARD LVCMOS33} [get_ports io_led[0]]
set_property -dict {PACKAGE_PIN N2 IOSTANDARD LVCMOS33} [get_ports io_led[1]]
set_property -dict {PACKAGE_PIN M6 IOSTANDARD LVCMOS33} [get_ports io_led[2]]
set_property -dict {PACKAGE_PIN M5 IOSTANDARD LVCMOS33} [get_ports io_led[3]]
set_clock_groups -name sample -asynchronous -group [get_clocks clkin] -group [get_clocks -of_objects [get_pins i_clk/inst/mmcm_adv_inst/CLKOUT0]] -group [get_clocks -of_objects [get_pins i_clk/inst/mmcm_adv_inst/CLKOUT1]]