让spi上行写入sram的数据保持稳定

2024-12-03 15:11:07 +08:00
parent 394854cdce
commit 77365c59d9
1 changed files with 1 additions and 1 deletions
--- a/src/main/scala/backBoard/SpiSlv.scala
+++ b/src/main/scala/backBoard/SpiSlv.scala
@@ -47,7 +47,7 @@ trait BackBoardSpiSlv{ this: BackBoardSlvLocal =>
  spiRegDown.io.enr := spiCmd === 0.U & isSckPosedgeNext(0)

  spiRegUp.io.addrw := Cat(pageSel, byteSel - 1.U)
-  spiRegUp.io.dataw := exReg_100M
+  spiRegUp.io.dataw := withClockAndReset( clk100M.asClock, reset ){ RegEnable(exReg_100M, bitSel === 0.U) }
  spiRegUp.io.enw   := isSckPosedgeNext(1) & ~shiftCSn(1+1) & bitSel === 0.U & spiCmd === 1.U
     
  withClockAndReset( clk100M.asClock, reset ){//100M