From 77365c59d913deec8375af6dc9a80cf713b8ddb8 Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Tue, 3 Dec 2024 15:11:07 +0800 Subject: [PATCH] =?UTF-8?q?=E8=AE=A9spi=E4=B8=8A=E8=A1=8C=E5=86=99?= =?UTF-8?q?=E5=85=A5sram=E7=9A=84=E6=95=B0=E6=8D=AE=E4=BF=9D=E6=8C=81?= =?UTF-8?q?=E7=A8=B3=E5=AE=9A?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/SpiSlv.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/backBoard/SpiSlv.scala b/src/main/scala/backBoard/SpiSlv.scala index 903afc5..db1087b 100644 --- a/src/main/scala/backBoard/SpiSlv.scala +++ b/src/main/scala/backBoard/SpiSlv.scala @@ -47,7 +47,7 @@ trait BackBoardSpiSlv{ this: BackBoardSlvLocal => spiRegDown.io.enr := spiCmd === 0.U & isSckPosedgeNext(0) spiRegUp.io.addrw := Cat(pageSel, byteSel - 1.U) - spiRegUp.io.dataw := exReg_100M + spiRegUp.io.dataw := withClockAndReset( clk100M.asClock, reset ){ RegEnable(exReg_100M, bitSel === 0.U) } spiRegUp.io.enw := isSckPosedgeNext(1) & ~shiftCSn(1+1) & bitSel === 0.U & spiCmd === 1.U withClockAndReset( clk100M.asClock, reset ){//100M