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让spi上行写入sram的数据保持稳定

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RuigeLee
2024-12-03 15:11:07 +08:00
parent 394854cdce
commit 77365c59d9
1 changed files with 1 additions and 1 deletions
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src/main/scala/backBoard/SpiSlv.scala
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@@ -47,7 +47,7 @@ trait BackBoardSpiSlv{ this: BackBoardSlvLocal =>
spiRegDown.io.enr := spiCmd === 0.U & isSckPosedgeNext(0) spiRegDown.io.enr := spiCmd === 0.U & isSckPosedgeNext(0)
spiRegUp.io.addrw := Cat(pageSel, byteSel - 1.U) spiRegUp.io.addrw := Cat(pageSel, byteSel - 1.U)
spiRegUp.io.dataw := exReg_100M spiRegUp.io.dataw := withClockAndReset( clk100M.asClock, reset ){ RegEnable(exReg_100M, bitSel === 0.U) }
spiRegUp.io.enw := isSckPosedgeNext(1) & ~shiftCSn(1+1) & bitSel === 0.U & spiCmd === 1.U spiRegUp.io.enw := isSckPosedgeNext(1) & ~shiftCSn(1+1) & bitSel === 0.U & spiCmd === 1.U
withClockAndReset( clk100M.asClock, reset ){//100M withClockAndReset( clk100M.asClock, reset ){//100M