sck下降沿操作前移到上升沿后两拍

2024-07-03 16:36:45 +08:00
parent 17dd970d47
commit 73bfd7e109
2 changed files with 13 additions and 11 deletions
--- a/src/main/verilog/spi_top.v
+++ b/src/main/verilog/spi_top.v
@@ -24,7 +24,9 @@ module spi_top(
  input         sck,
  input         mosi,
  output        miso,
-  input         csn
+  input         csn,
+
+  output        interrupt

 );

@@ -310,7 +312,7 @@ SpiSlv i_spiSlv(
  .spi_miso(miso),
  .spi_csn(csn),
  .clk100MIO(clk_100m_a),
-  .interrupt()
+  .interrupt(interrupt)
 );