diff --git a/src/main/scala/backBoard/SpiSlv.scala b/src/main/scala/backBoard/SpiSlv.scala
index 467d487..dc5a1ff 100644
--- a/src/main/scala/backBoard/SpiSlv.scala
+++ b/src/main/scala/backBoard/SpiSlv.scala
@@ -31,8 +31,8 @@ trait BackBoardSpiSlv{ this: BackBoardSlvLocal =>
   val shiftMOSI = withClockAndReset( clk100M.asClock, reset ){ ShiftRegisters(mosi, 3) }
 
 
-  val isSckPosedge = ~shiftSCK(2) & shiftSCK(1)
-  val isSckNegedge = shiftSCK(2) & ~shiftSCK(1)
+  val isSckPosedge     = ~shiftSCK(2) & shiftSCK(1)
+  val isSckPosedgeNext = withClockAndReset( clk100M.asClock, reset ){ ShiftRegisters(isSckPosedge, 2, false.B, true.B) }
 
 
   val exReg_100M = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(8.W)) }
@@ -46,11 +46,11 @@ trait BackBoardSpiSlv{ this: BackBoardSlvLocal =>
 
 
   spiRegDown.io.addrr := Cat(pageSel, byteSel)
-  spiRegDown.io.enr := spiCmd === 0.U
+  spiRegDown.io.enr := spiCmd === 0.U & isSckPosedgeNext(0)
 
   spiRegUp.io.addrw := Cat(pageSel, byteSel - 1.U)
   spiRegUp.io.dataw := exReg_100M
-  spiRegUp.io.enw   := isSckNegedge & ~shiftCSn(1+1) & bitSel === 0.U & spiCmd === 1.U
+  spiRegUp.io.enw   := isSckPosedgeNext(1) & ~shiftCSn(1+1) & bitSel === 0.U & spiCmd === 1.U
      
   withClockAndReset( clk100M.asClock, reset ){//100M
 
@@ -71,7 +71,7 @@ trait BackBoardSpiSlv{ this: BackBoardSlvLocal =>
       exReg_100M := upReg(0)
     } .elsewhen( isSckPosedge & ~shiftCSn(1) & byteSel === 0.U ){
       cmd_100M := Cat( cmd_100M(6,0), shiftMOSI(1) )
-    } .elsewhen( isSckNegedge & ~shiftCSn(1) & bitSel === 0.U ){
+    } .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(1) & bitSel === 0.U ){
       when( byteSel === 1.U ){
         exReg_100M := upReg(1)
       } .elsewhen( spiCmd === 2.U & byteSel === 2.U ){
@@ -81,13 +81,13 @@ trait BackBoardSpiSlv{ this: BackBoardSlvLocal =>
       } .elsewhen( spiCmd === 0.U & (byteSel =/= 0.U | byteSel =/= 1.U) ){
         exReg_100M := spiRegDown.io.datar
       }
-    } .elsewhen( isSckPosedge & ~shiftCSn(1) & byteSel =/= 0.U ){
+    } .elsewhen( isSckPosedge & ~shiftCSn(1) & (byteSel =/= 0.U | byteSel =/= 1.U) ){
       exReg_100M := Cat( exReg_100M(6 ,0), shiftMOSI(1) )
     }
 
-    when(  isSckNegedge & ~shiftCSn(1) & byteSel === 3.U & bitSel === 0.U & spiCmd === 3.U ){
+    when(  isSckPosedgeNext(1) & ~shiftCSn(1) & byteSel === 3.U & bitSel === 0.U & spiCmd === 3.U ){
       exMask_100M := Cat( exReg_100M, exMask_100M(7,0) )
-    } .elsewhen(  isSckNegedge & ~shiftCSn(1) & byteSel === 4.U & bitSel === 0.U & spiCmd === 3.U ){
+    } .elsewhen(  isSckPosedgeNext(1) & ~shiftCSn(1) & byteSel === 4.U & bitSel === 0.U & spiCmd === 3.U ){
       exMask_100M := Cat( exMask_100M(15,8), exReg_100M )
     }
 
@@ -128,7 +128,7 @@ with BackBoardSpiSlv{
 
   
 
-  spiRegDown.io.enw := io.lvdsSlv.downstream_rx_data_valid & downCnt =/= 0.U
+  spiRegDown.io.enw := io.lvdsSlv.downstream_rx_data_valid & (downCnt =/= 0.U | downCnt =/= 1.U)
   spiRegDown.io.dataw := io.lvdsSlv.downstream_rx_data_out
   spiRegDown.io.addrw := Cat( downRegTemp(0)(3,0), downCnt(4,0))
 
diff --git a/src/main/verilog/spi_top.v b/src/main/verilog/spi_top.v
index 3a2b6ef..9cdaf2a 100644
--- a/src/main/verilog/spi_top.v
+++ b/src/main/verilog/spi_top.v
@@ -24,7 +24,9 @@ module spi_top(
   input         sck,
   input         mosi,
   output        miso,
-  input         csn
+  input         csn,
+
+  output        interrupt
 
 );
 
@@ -310,7 +312,7 @@ SpiSlv i_spiSlv(
   .spi_miso(miso),
   .spi_csn(csn),
   .clk100MIO(clk_100m_a),
-  .interrupt()
+  .interrupt(interrupt)
 );