ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

sck下降沿操作前移到上升沿后两拍

Browse Source
This commit is contained in:
RuigeLee
2024-07-03 16:36:45 +08:00
parent 17dd970d47
commit 73bfd7e109
2 changed files with 13 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
src/main/scala/backBoard/SpiSlv.scala
View File

@@ -31,8 +31,8 @@ trait BackBoardSpiSlv{ this: BackBoardSlvLocal =>
val shiftMOSI = withClockAndReset( clk100M.asClock, reset ){ ShiftRegisters(mosi, 3) }
val isSckPosedge = ~shiftSCK(2) & shiftSCK(1)
val isSckNegedge = shiftSCK(2) & ~shiftSCK(1)
val isSckPosedge = ~shiftSCK(2) & shiftSCK(1)
val isSckPosedgeNext = withClockAndReset( clk100M.asClock, reset ){ ShiftRegisters(isSckPosedge, 2, false.B, true.B) }
val exReg_100M = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(8.W)) }
@@ -46,11 +46,11 @@ trait BackBoardSpiSlv{ this: BackBoardSlvLocal =>
spiRegDown.io.addrr := Cat(pageSel, byteSel)
spiRegDown.io.enr := spiCmd === 0.U
spiRegDown.io.enr := spiCmd === 0.U & isSckPosedgeNext(0)
spiRegUp.io.addrw := Cat(pageSel, byteSel - 1.U)
spiRegUp.io.dataw := exReg_100M
spiRegUp.io.enw := isSckNegedge & ~shiftCSn(1+1) & bitSel === 0.U & spiCmd === 1.U
spiRegUp.io.enw := isSckPosedgeNext(1) & ~shiftCSn(1+1) & bitSel === 0.U & spiCmd === 1.U
withClockAndReset( clk100M.asClock, reset ){//100M
@@ -71,7 +71,7 @@ trait BackBoardSpiSlv{ this: BackBoardSlvLocal =>
exReg_100M := upReg(0)
} .elsewhen( isSckPosedge & ~shiftCSn(1) & byteSel === 0.U ){
cmd_100M := Cat( cmd_100M(6,0), shiftMOSI(1) )
} .elsewhen( isSckNegedge & ~shiftCSn(1) & bitSel === 0.U ){
} .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(1) & bitSel === 0.U ){
when( byteSel === 1.U ){
exReg_100M := upReg(1)
} .elsewhen( spiCmd === 2.U & byteSel === 2.U ){
@@ -81,13 +81,13 @@ trait BackBoardSpiSlv{ this: BackBoardSlvLocal =>
} .elsewhen( spiCmd === 0.U & (byteSel =/= 0.U | byteSel =/= 1.U) ){
exReg_100M := spiRegDown.io.datar
}
} .elsewhen( isSckPosedge & ~shiftCSn(1) & byteSel =/= 0.U ){
} .elsewhen( isSckPosedge & ~shiftCSn(1) & (byteSel =/= 0.U | byteSel =/= 1.U) ){
exReg_100M := Cat( exReg_100M(6 ,0), shiftMOSI(1) )
}
when( isSckNegedge & ~shiftCSn(1) & byteSel === 3.U & bitSel === 0.U & spiCmd === 3.U ){
when( isSckPosedgeNext(1) & ~shiftCSn(1) & byteSel === 3.U & bitSel === 0.U & spiCmd === 3.U ){
exMask_100M := Cat( exReg_100M, exMask_100M(7,0) )
} .elsewhen( isSckNegedge & ~shiftCSn(1) & byteSel === 4.U & bitSel === 0.U & spiCmd === 3.U ){
} .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(1) & byteSel === 4.U & bitSel === 0.U & spiCmd === 3.U ){
exMask_100M := Cat( exMask_100M(15,8), exReg_100M )
}
@@ -128,7 +128,7 @@ with BackBoardSpiSlv{
spiRegDown.io.enw := io.lvdsSlv.downstream_rx_data_valid & downCnt =/= 0.U
spiRegDown.io.enw := io.lvdsSlv.downstream_rx_data_valid & (downCnt =/= 0.U | downCnt =/= 1.U)
spiRegDown.io.dataw := io.lvdsSlv.downstream_rx_data_out
spiRegDown.io.addrw := Cat( downRegTemp(0)(3,0), downCnt(4,0))