仿真，状态机错误

tb/cdrOut_tb.v

@@ -0,0 +1,113 @@
+`timescale 1 ns / 1 ps
+
+
+module CDROut_tb();
+
+
+
+
+    reg clock = 0;
+    reg reset = 1;
+
+    wire serDat;
+
+    wire       axis_ready;
+
+    reg       axis_valid = 0;
+    reg [7:0] axis_bits_tdata;
+    reg       axis_bits_tlast;
+    reg       axis_bits_tuser;
+
+
+
+    CDROut s_CDROut(
+    .clock(clock),
+    .reset(reset),
+
+    .io_axis_ready(axis_ready),
+    .io_axis_valid(axis_valid),
+    .io_axis_bits_tdata(axis_bits_tdata),
+    .io_axis_bits_tlast(axis_bits_tlast),
+    .io_axis_bits_tuser(axis_bits_tuser),
+    .io_serDat(serDat)
+    );
+
+
+
+
+
+initial begin
+    forever #20 clock = ~clock;
+end
+
+initial begin
+    # 100 reset = 1;
+    # 100 reset = 0;
+end
+
+
+reg [7:0] cnt = 0;
+
+
+    // always @(posedge clock) begin
+    //     if( cnt == 8'd0 ) begin
+    //         #2 axis_valid <= 1'b1;
+    //         #2 axis_bits_tdata <= cnt;
+    //         #2 axis_bits_tlast <= 1'b0;
+    //         #2 axis_bits_tuser <= 1'b0;
+    //         #2 cnt <= cnt + 8'd1;
+    //     end else begin
+    //         if( axis_valid & axis_ready ) begin
+    //             axis_valid <= 1'b0;
+    //         end else if( ~axis_valid ) begin
+    //             #2 axis_valid <= 1'b1;
+    //             if ( cnt == 8'd255 ) begin
+    //                 #2 axis_bits_tlast <= 1'b1;
+    //             end else begin
+    //                 #2 axis_bits_tlast <= 1'b0;
+    //                 #2 cnt <= cnt + 8'd1;
+    //             end
+    //         end
+    //     end
+    // end
+
+    always @(posedge clock) begin
+        if( cnt == 8'd0 ) begin
+            #2 axis_valid <= 1'b1;
+            #2 axis_bits_tdata <= cnt;
+            #2 axis_bits_tlast <= 1'b0;
+            #2 axis_bits_tuser <= 1'b0;
+            #2 cnt <= cnt + 8'd1;
+        end else begin
+            if( axis_valid & axis_ready ) begin
+                if ( axis_bits_tlast ) begin
+                    #2 axis_valid <= 1'b0;
+                    #2 axis_bits_tlast <= 1'b0;
+                end else begin
+                    #2 axis_bits_tdata <= cnt;
+                    #2 axis_bits_tuser <= 1'b0;
+                    if( cnt == 8'd31 ) begin
+                        #2 axis_bits_tlast <= 1'b1;
+                    end else begin
+                        #2 cnt <= cnt + 8'd1;
+                    end
+                end
+            end
+        end
+    end
+
+
+
+    initial begin
+        # 100000
+        $finish;
+
+    end
+
+    initial begin
+        $dumpfile("./build/wave.vcd"); //生成的vcd文件名称
+        $dumpvars(0, CDROut_tb);//tb模块名称
+    end
+
+
+endmodule