仿真，状态机错误

2024-09-10 18:39:35 +08:00
parent 0080705f0d
commit 7350f3bcf4
6 changed files with 835 additions and 1 deletions
--- a/src/test/scala/gcd/test.scala
+++ b/src/test/scala/gcd/test.scala
@@ -38,6 +38,9 @@ object testModule extends App {
    ))   


+   (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-E", "verilog" ) ++ args, Seq(
+      ChiselGeneratorAnnotation(() => { new CDROut })
+    ))   

  // (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
  //     ChiselGeneratorAnnotation(() => { new BackPlaneChainTest })