仿真，状态机错误
This commit is contained in:
RuigeLee
105
src/main/scala/backBoard/ebus/CDROut.scala
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105
src/main/scala/backBoard/ebus/CDROut.scala
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@@ -0,0 +1,105 @@
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package BACK
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import chisel3._
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import chisel3.util._
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class AXIS_Bundle extends Bundle{
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val tdata = UInt(8.W)
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val tlast = Bool()
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val tuser = Bool()
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}
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//work in 100MHZ
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class CDROutIO extends Bundle{
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val axis = Flipped(Decoupled(new AXIS_Bundle))
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val serDat = Output(Bool())
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}
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class CDROut extends Module{
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val io: CDROutIO = IO(new CDROutIO)
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val crcUnit = Module(new crc32_8)
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def STATE_IDLE = 0.U
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def STATE_PREAMBLE = 1.U
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def STATE_PAYLOAD = 2.U
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def STATE_FCS = 3.U
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val ETH_PRE = "h55".U
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val ETH_SFD = "hD5".U
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val stateNext = Wire(UInt(2.W))
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val stateCurr = RegNext( stateNext, 0.U )
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val bitCnt = Reg(UInt(3.W))
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val byteCnt = Reg(UInt(16.W))
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val crcOut = crcUnit.io.crc
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val reset_crc = stateCurr === STATE_IDLE
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crcUnit.reset := reset.asBool | reset_crc
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crcUnit.io.dataIn := io.axis.bits.tdata
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crcUnit.io.isEnable := io.axis.fire
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val shiftData = RegInit(0.U(8.W))
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stateNext := Mux1H(Seq(
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(stateCurr === STATE_IDLE) -> ( Mux( io.axis.valid, STATE_PREAMBLE, STATE_IDLE )),
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(stateCurr === STATE_PREAMBLE) -> ( Mux( byteCnt === 7.U & bitCnt === 7.U, STATE_PAYLOAD, STATE_PREAMBLE )),
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(stateCurr === STATE_PAYLOAD) -> ( Mux( io.axis.fire, Mux( io.axis.bits.tlast, STATE_FCS, STATE_PAYLOAD ), STATE_FCS ) ),
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(stateCurr === STATE_FCS) -> ( Mux( byteCnt === 3.U & bitCnt === 7.U, STATE_FCS, STATE_IDLE )),
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))
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io.serDat := shiftData.extract(7)
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io.axis.ready :=
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bitCnt === 7.U & (
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(stateCurr === STATE_PREAMBLE & byteCnt === 7.U) |
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(stateCurr === STATE_PAYLOAD)
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)
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when( stateCurr === STATE_IDLE & stateNext === STATE_PREAMBLE){ //PRE
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shiftData := ETH_PRE
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} .otherwise{
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when( bitCnt =/= 7.U ){
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shiftData := shiftData << 1
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} .otherwise{ //bitCnt === 7.U
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when( stateCurr === STATE_PREAMBLE ){
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shiftData := MuxCase( ETH_PRE, Array(
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( byteCnt === 6.U ) -> ETH_SFD,
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( byteCnt === 7.U ) -> io.axis.bits.tdata,
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))
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} .elsewhen( stateCurr === STATE_PAYLOAD ){
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shiftData := io.axis.bits.tdata
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} .elsewhen( stateCurr === STATE_FCS ){
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shiftData := Mux1H(Seq(
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( byteCnt === 0.U) -> ~crcOut( 7,0),
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( byteCnt === 1.U) -> ~crcOut(15,8),
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( byteCnt === 2.U) -> ~crcOut(23,16),
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( byteCnt === 3.U) -> ~crcOut(31,24),
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))
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}
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}
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}
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when( stateCurr === STATE_IDLE ){ //PRE
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bitCnt := 0.U
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} .otherwise{
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bitCnt := bitCnt + 1.U
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}
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when( stateNext =/= stateCurr ){
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byteCnt := 0.U
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} .elsewhen( bitCnt === 7.U ){
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byteCnt := byteCnt + 1.U
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}
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}
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141
src/main/scala/backBoard/ebus/crc32.scala
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141
src/main/scala/backBoard/ebus/crc32.scala
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@@ -0,0 +1,141 @@
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package BACK
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import chisel3._
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import chisel3.util._
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// module eth_crc (Clk, Reset, Data, Enable, Initialize, Crc, CrcError);
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// input Clk;
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// input Reset;
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// input [3:0] Data;
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// input Enable;
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// input Initialize;
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// output [31:0] Crc;
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// output CrcError;
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// reg [31:0] Crc;
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// wire [31:0] CrcNext;
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// assign CrcNext[0] = Enable & (Data[0] ^ Crc[28]);
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// assign CrcNext[1] = Enable & (Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29]);
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// assign CrcNext[2] = Enable & (Data[2] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[30]);
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// assign CrcNext[3] = Enable & (Data[3] ^ Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30] ^ Crc[31]);
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// assign CrcNext[4] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[0];
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// assign CrcNext[5] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[1];
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// assign CrcNext[6] = (Enable & (Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30])) ^ Crc[ 2];
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// assign CrcNext[7] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[3];
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// assign CrcNext[8] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[4];
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// assign CrcNext[9] = (Enable & (Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30])) ^ Crc[5];
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// assign CrcNext[10] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[6];
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// assign CrcNext[11] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[7];
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// assign CrcNext[12] = (Enable & (Data[2] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[30])) ^ Crc[8];
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// assign CrcNext[13] = (Enable & (Data[3] ^ Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30] ^ Crc[31])) ^ Crc[9];
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// assign CrcNext[14] = (Enable & (Data[3] ^ Data[2] ^ Crc[30] ^ Crc[31])) ^ Crc[10];
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// assign CrcNext[15] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[11];
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// assign CrcNext[16] = (Enable & (Data[0] ^ Crc[28])) ^ Crc[12];
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// assign CrcNext[17] = (Enable & (Data[1] ^ Crc[29])) ^ Crc[13];
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// assign CrcNext[18] = (Enable & (Data[2] ^ Crc[30])) ^ Crc[14];
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// assign CrcNext[19] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[15];
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// assign CrcNext[20] = Crc[16];
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// assign CrcNext[21] = Crc[17];
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// assign CrcNext[22] = (Enable & (Data[0] ^ Crc[28])) ^ Crc[18];
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// assign CrcNext[23] = (Enable & (Data[1] ^ Data[0] ^ Crc[29] ^ Crc[28])) ^ Crc[19];
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// assign CrcNext[24] = (Enable & (Data[2] ^ Data[1] ^ Crc[30] ^ Crc[29])) ^ Crc[20];
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// assign CrcNext[25] = (Enable & (Data[3] ^ Data[2] ^ Crc[31] ^ Crc[30])) ^ Crc[21];
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// assign CrcNext[26] = (Enable & (Data[3] ^ Data[0] ^ Crc[31] ^ Crc[28])) ^ Crc[22];
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// assign CrcNext[27] = (Enable & (Data[1] ^ Crc[29])) ^ Crc[23];
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// assign CrcNext[28] = (Enable & (Data[2] ^ Crc[30])) ^ Crc[24];
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// assign CrcNext[29] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[25];
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// assign CrcNext[30] = Crc[26];
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// assign CrcNext[31] = Crc[27];
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// always @ (posedge Clk or posedge Reset)
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// begin
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// if (Reset)
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// Crc <= 32'hffffffff;
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// else
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// if(Initialize)
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// Crc <= 32'hffffffff;
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// else
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// Crc <= CrcNext;
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// end
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// assign CrcError = Crc[31:0] != 32'hc704dd7b; // CRC not equal to magic number
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// endmodule
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//-----------------------------------------------------------------------------
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// Copyright (C) 2009 OutputLogic.com
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// This source file may be used and distributed without restriction
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// provided that this copyright statement is not removed from the file
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// and that any derivative work contains the original copyright notice
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// and the associated disclaimer.
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//
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// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
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// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
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// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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//-----------------------------------------------------------------------------
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// CRC module for data[7:0] , crc[31:0]=1+x^1+x^2+x^4+x^5+x^7+x^8+x^10+x^11+x^12+x^16+x^22+x^23+x^26+x^32;
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//-----------------------------------------------------------------------------
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class crc32_8() extends Module{
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class crc32IO_Bundle extends Bundle{
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val isEnable = Input(Bool())
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val dataIn = Input(UInt(8.W))
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val crc = Output(UInt(32.W))
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}
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val io = IO( new crc32IO_Bundle )
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// val LFSR_POLY = "h4c11db7".U
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val lfsr_c = for( i <- 0 until 32 ) yield Wire(Bool())
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val lfsr_q = for( i <- 0 until 32 ) yield RegEnable( lfsr_c(i), true.B, io.isEnable )
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io.crc := Cat( lfsr_q.reverse )
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lfsr_c( 0) := lfsr_q(24) ^ lfsr_q(30) ^ io.dataIn(0) ^ io.dataIn(6)
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lfsr_c( 1) := lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(30) ^ lfsr_q(31) ^ io.dataIn(0) ^ io.dataIn(1) ^ io.dataIn(6) ^ io.dataIn(7)
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lfsr_c( 2) := lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(30) ^ lfsr_q(31) ^ io.dataIn(0) ^ io.dataIn(1) ^ io.dataIn(2) ^ io.dataIn(6) ^ io.dataIn(7)
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lfsr_c( 3) := lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(31) ^ io.dataIn(1) ^ io.dataIn(2) ^ io.dataIn(3) ^ io.dataIn(7)
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lfsr_c( 4) := lfsr_q(24) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(28) ^ lfsr_q(30) ^ io.dataIn(0) ^ io.dataIn(2) ^ io.dataIn(3) ^ io.dataIn(4) ^ io.dataIn(6)
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lfsr_c( 5) := lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(27) ^ lfsr_q(28) ^ lfsr_q(29) ^ lfsr_q(30) ^ lfsr_q(31) ^ io.dataIn(0) ^ io.dataIn(1) ^ io.dataIn(3) ^ io.dataIn(4) ^ io.dataIn(5) ^ io.dataIn(6) ^ io.dataIn(7)
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lfsr_c( 6) := lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(28) ^ lfsr_q(29) ^ lfsr_q(30) ^ lfsr_q(31) ^ io.dataIn(1) ^ io.dataIn(2) ^ io.dataIn(4) ^ io.dataIn(5) ^ io.dataIn(6) ^ io.dataIn(7)
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lfsr_c( 7) := lfsr_q(24) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(29) ^ lfsr_q(31) ^ io.dataIn(0) ^ io.dataIn(2) ^ io.dataIn(3) ^ io.dataIn(5) ^ io.dataIn(7)
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lfsr_c( 8) := lfsr_q( 0) ^ lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(27) ^ lfsr_q(28) ^ io.dataIn(0) ^ io.dataIn(1) ^ io.dataIn(3) ^ io.dataIn(4)
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lfsr_c( 9) := lfsr_q( 1) ^ lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(28) ^ lfsr_q(29) ^ io.dataIn(1) ^ io.dataIn(2) ^ io.dataIn(4) ^ io.dataIn(5)
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lfsr_c(10) := lfsr_q( 2) ^ lfsr_q(24) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(29) ^ io.dataIn(0) ^ io.dataIn(2) ^ io.dataIn(3) ^ io.dataIn(5)
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lfsr_c(11) := lfsr_q( 3) ^ lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(27) ^ lfsr_q(28) ^ io.dataIn(0) ^ io.dataIn(1) ^ io.dataIn(3) ^ io.dataIn(4)
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lfsr_c(12) := lfsr_q( 4) ^ lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(28) ^ lfsr_q(29) ^ lfsr_q(30) ^ io.dataIn(0) ^ io.dataIn(1) ^ io.dataIn(2) ^ io.dataIn(4) ^ io.dataIn(5) ^ io.dataIn(6)
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lfsr_c(13) := lfsr_q( 5) ^ lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(29) ^ lfsr_q(30) ^ lfsr_q(31) ^ io.dataIn(1) ^ io.dataIn(2) ^ io.dataIn(3) ^ io.dataIn(5) ^ io.dataIn(6) ^ io.dataIn(7)
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lfsr_c(14) := lfsr_q( 6) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(28) ^ lfsr_q(30) ^ lfsr_q(31) ^ io.dataIn(2) ^ io.dataIn(3) ^ io.dataIn(4) ^ io.dataIn(6) ^ io.dataIn(7)
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lfsr_c(15) := lfsr_q( 7) ^ lfsr_q(27) ^ lfsr_q(28) ^ lfsr_q(29) ^ lfsr_q(31) ^ io.dataIn(3) ^ io.dataIn(4) ^ io.dataIn(5) ^ io.dataIn(7)
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lfsr_c(16) := lfsr_q( 8) ^ lfsr_q(24) ^ lfsr_q(28) ^ lfsr_q(29) ^ io.dataIn(0) ^ io.dataIn(4) ^ io.dataIn(5)
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lfsr_c(17) := lfsr_q( 9) ^ lfsr_q(25) ^ lfsr_q(29) ^ lfsr_q(30) ^ io.dataIn(1) ^ io.dataIn(5) ^ io.dataIn(6)
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lfsr_c(18) := lfsr_q(10) ^ lfsr_q(26) ^ lfsr_q(30) ^ lfsr_q(31) ^ io.dataIn(2) ^ io.dataIn(6) ^ io.dataIn(7)
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lfsr_c(19) := lfsr_q(11) ^ lfsr_q(27) ^ lfsr_q(31) ^ io.dataIn(3) ^ io.dataIn(7)
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lfsr_c(20) := lfsr_q(12) ^ lfsr_q(28) ^ io.dataIn(4)
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lfsr_c(21) := lfsr_q(13) ^ lfsr_q(29) ^ io.dataIn(5)
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lfsr_c(22) := lfsr_q(14) ^ lfsr_q(24) ^ io.dataIn(0)
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lfsr_c(23) := lfsr_q(15) ^ lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(30) ^ io.dataIn(0) ^ io.dataIn(1) ^ io.dataIn(6)
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lfsr_c(24) := lfsr_q(16) ^ lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(31) ^ io.dataIn(1) ^ io.dataIn(2) ^ io.dataIn(7)
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lfsr_c(25) := lfsr_q(17) ^ lfsr_q(26) ^ lfsr_q(27) ^ io.dataIn(2) ^ io.dataIn(3)
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lfsr_c(26) := lfsr_q(18) ^ lfsr_q(24) ^ lfsr_q(27) ^ lfsr_q(28) ^ lfsr_q(30) ^ io.dataIn(0) ^ io.dataIn(3) ^ io.dataIn(4) ^ io.dataIn(6)
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lfsr_c(27) := lfsr_q(19) ^ lfsr_q(25) ^ lfsr_q(28) ^ lfsr_q(29) ^ lfsr_q(31) ^ io.dataIn(1) ^ io.dataIn(4) ^ io.dataIn(5) ^ io.dataIn(7)
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lfsr_c(28) := lfsr_q(20) ^ lfsr_q(26) ^ lfsr_q(29) ^ lfsr_q(30) ^ io.dataIn(2) ^ io.dataIn(5) ^ io.dataIn(6)
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lfsr_c(29) := lfsr_q(21) ^ lfsr_q(27) ^ lfsr_q(30) ^ lfsr_q(31) ^ io.dataIn(3) ^ io.dataIn(6) ^ io.dataIn(7)
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lfsr_c(30) := lfsr_q(22) ^ lfsr_q(28) ^ lfsr_q(31) ^ io.dataIn(4) ^ io.dataIn(7)
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lfsr_c(31) := lfsr_q(23) ^ lfsr_q(29) ^ io.dataIn(5)
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}
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@@ -38,6 +38,9 @@ object testModule extends App {
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))
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(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-E", "verilog" ) ++ args, Seq(
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ChiselGeneratorAnnotation(() => { new CDROut })
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))
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// (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
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// ChiselGeneratorAnnotation(() => { new BackPlaneChainTest })
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