仿真，状态机错误

2024-09-10 18:39:35 +08:00
parent 0080705f0d
commit 7350f3bcf4
6 changed files with 835 additions and 1 deletions
--- a/14
+++ b/14
@@ -1,5 +1,5 @@

-.PHONY: compile
+.PHONY: compile tb wave

 compile:
 	rm -rf ./generated/
@@ -116,4 +116,16 @@ VSimBack:



+tb:
+	cp ./generated/cdr/CDROut.v ./tb
+	iverilog -Wall \
+	-o ./build/wave.iverilog  \
+	-y ./tb  \
+	-I ./tb  \
+	-D RANDOMIZE_REG_INIT \
+	./tb/cdrOut_tb.v 
+	vvp  -N ./build/wave.iverilog -lxt2
+
+vcd:
+	gtkwave ./build/wave.vcd &