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复位将在spi写操作0x40地址任意值后16拍触发，引出为外部输出io

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This commit is contained in:
Ruige Lee
2025-05-21 16:04:39 +08:00
parent f8712482ee
commit 72e725a11f
3 changed files with 35 additions and 43 deletions
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37
src/main/scala/backBoard/shin/Interface.scala
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@@ -90,18 +90,13 @@ class SlaveRegisterBundle extends Bundle{
// })
// val downTimeStamp = UInt(64.W) //下行本地时间戳寄存器
// val upTimeStamp = UInt(64.W) //上行本地时间戳寄存器
// val mstTimeStamp = UInt(64.W) //主站时间戳
// val dcSyncEnable = Bool()
// val dcSyncWidth = UInt(16.W)
val localDevIndex = UInt(16.W)
//链路寄存器组
// val isDevOnLeft = UInt(2.W)
val isDevOnLeftModify = Bool()
val indexOfLeftDev = UInt(14.W)
val isDevOnRight = UInt(2.W)
@@ -109,15 +104,6 @@ class SlaveRegisterBundle extends Bundle{
val indexOfRightDev = UInt(14.W)
// val downTimeStamp = Reg(UInt(64.W)) //下行本地时间戳寄存器
// val upTimeStamp = Reg(UInt(64.W)) //上行本地时间戳寄存器
// val mstDeltaTimeStamp = Reg(UInt(32.W)); io.mstDeltaTimeStamp := mstDeltaTimeStamp //主站时间戳差值
// val mstSlvDeltaTimeStamp = Reg(UInt(32.W)) //主发从接时间差(中间变量)
// val deltaMstSlvDeltaTimeStamp = Reg(UInt(32.W)) //主差从差时间差(中间变量)
// val mstTimeStamp = UInt(64.W) //主站时间戳
val slvDeltaTime = UInt(32.W) //从站时间戳差值
val deltaFinal = UInt(32.W) //当前时间戳与主站时间差
val recoTimeStamp = UInt(64.W) //时钟补偿寄存器
@@ -133,13 +119,6 @@ class SlaveRegisterBundle extends Bundle{
// recoTimeStamp = io.timeStamp + deltaFinal
// recoTimeStamp = io.timeStamp + mstSlvDeltaTimeStamp + deltaMstSlvDeltaTimeStamp
// recoTimeStamp = io.timeStamp + mstTimeStamp - downTimeStamp + (mstDeltaTimeStamp - slvDeltaTimeStamp ) >> 1
// recoTimeStamp = io.timeStamp + mstTimeStamp - downTimeStamp + (mstDeltaTimeStamp - (upTimeStamp - downTimeStamp)) >> 1
}
@@ -189,6 +168,8 @@ class InterfaceIO extends Bundle{
val deltaFinal = Input(UInt(32.W))
val sync = Output(Vec(4, Bool()))
val isSoftReset = Output(Bool())
}
@@ -662,12 +643,7 @@ trait InterfaceSync{ this: InterfaceBase =>
cReg.timeStamp := RegNext( cReg.timeStamp + 1.U, 0.U )
cReg.mstDeltaTime := io.mstDeltaTime
// Cat(
//RegEnable( dataw, 0.U, isEnW & addrw === "h1d3".U ),
//RegEnable( dataw, 0.U, isEnW & addrw === "h1d2".U ),
//RegEnable( dataw, 0.U, isEnW & addrw === "h1d1".U ),
//RegEnable( dataw, 0.U, isEnW & addrw === "h1d0".U ),
// )
// sReg.mstTimeStamp := io.mstTimeStamp
sReg.deltaFinal := io.deltaFinal
@@ -727,11 +703,16 @@ trait InterfaceSync{ this: InterfaceBase =>
}
trait InterfaceSystem{ this: InterfaceBase =>
io.isSoftReset := ShiftRegister( isEnW & addrw === "h40".U, 16, false.B, true.B )
}
class Interface extends InterfaceBase
with InterfaceMCUop
with InterfaceCheckSM
with InterfaceLVDSop
with InterfaceSync
with InterfaceSystem
{