diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index f1a3388..04b2282 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -90,18 +90,13 @@ class SlaveRegisterBundle extends Bundle{
   // })
 
 
-  // val downTimeStamp = UInt(64.W) //下行本地时间戳寄存器 
-  // val upTimeStamp   = UInt(64.W) //上行本地时间戳寄存器
-  // val mstTimeStamp  = UInt(64.W) //主站时间戳
 
-  // val dcSyncEnable = Bool()
-  // val dcSyncWidth  = UInt(16.W)
 
 
   val localDevIndex = UInt(16.W)
 
   //链路寄存器组
-  // val isDevOnLeft = UInt(2.W)
+
   val isDevOnLeftModify = Bool()
   val indexOfLeftDev = UInt(14.W)
   val isDevOnRight = UInt(2.W)
@@ -109,15 +104,6 @@ class SlaveRegisterBundle extends Bundle{
   val indexOfRightDev = UInt(14.W)
 
 
-  // val downTimeStamp = Reg(UInt(64.W)) //下行本地时间戳寄存器 
-  // val upTimeStamp   = Reg(UInt(64.W)) //上行本地时间戳寄存器
-  // val mstDeltaTimeStamp = Reg(UInt(32.W)); io.mstDeltaTimeStamp := mstDeltaTimeStamp //主站时间戳差值
-
-  // val mstSlvDeltaTimeStamp = Reg(UInt(32.W)) //主发从接时间差(中间变量)
-  // val deltaMstSlvDeltaTimeStamp = Reg(UInt(32.W)) //主差从差时间差(中间变量)
-
-
-  // val mstTimeStamp  = UInt(64.W) //主站时间戳
   val slvDeltaTime  = UInt(32.W) //从站时间戳差值
   val deltaFinal    = UInt(32.W) //当前时间戳与主站时间差
   val recoTimeStamp = UInt(64.W) //时钟补偿寄存器
@@ -133,13 +119,6 @@ class SlaveRegisterBundle extends Bundle{
 
 
 
-
-  // recoTimeStamp = io.timeStamp + deltaFinal
-  // recoTimeStamp = io.timeStamp + mstSlvDeltaTimeStamp         + deltaMstSlvDeltaTimeStamp
-  // recoTimeStamp = io.timeStamp + mstTimeStamp - downTimeStamp + (mstDeltaTimeStamp - slvDeltaTimeStamp            ) >> 1
-  // recoTimeStamp = io.timeStamp + mstTimeStamp - downTimeStamp + (mstDeltaTimeStamp - (upTimeStamp - downTimeStamp)) >> 1
-
-
 }
 
 
@@ -189,6 +168,8 @@ class InterfaceIO extends Bundle{
   val deltaFinal = Input(UInt(32.W))
 
   val sync = Output(Vec(4, Bool()))
+
+  val isSoftReset = Output(Bool())
 }
 
 
@@ -662,12 +643,7 @@ trait InterfaceSync{ this: InterfaceBase =>
   cReg.timeStamp := RegNext( cReg.timeStamp + 1.U, 0.U )
 
   cReg.mstDeltaTime := io.mstDeltaTime
-    // Cat(
-      //RegEnable( dataw, 0.U, isEnW & addrw === "h1d3".U ),
-      //RegEnable( dataw, 0.U, isEnW & addrw === "h1d2".U ),
-      //RegEnable( dataw, 0.U, isEnW & addrw === "h1d1".U ),
-      //RegEnable( dataw, 0.U, isEnW & addrw === "h1d0".U ),
-    // )
+
 
   // sReg.mstTimeStamp := io.mstTimeStamp
   sReg.deltaFinal := io.deltaFinal
@@ -727,11 +703,16 @@ trait InterfaceSync{ this: InterfaceBase =>
 
 }
 
+trait InterfaceSystem{ this: InterfaceBase =>
+  io.isSoftReset := ShiftRegister( isEnW & addrw === "h40".U, 16, false.B, true.B )
+}
+
 class Interface extends InterfaceBase
 with InterfaceMCUop
 with InterfaceCheckSM
 with InterfaceLVDSop
 with InterfaceSync
+with InterfaceSystem
 {
 
 
diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala
index fd75bb4..72bc295 100644
--- a/src/main/scala/backBoard/shin/ShinTop.scala
+++ b/src/main/scala/backBoard/shin/ShinTop.scala
@@ -43,6 +43,8 @@ class ShinTopIO extends Bundle{
 
   val iSync = Output(Vec(4, Bool()))
   val oSync = Output(Vec(4, Bool()))
+
+  val isSoftReset = Output(Bool())
 }
 
 
@@ -66,6 +68,8 @@ abstract class ShinTopBase extends Module{
 
   val interface = Module(new Interface)
 
+  io.isSoftReset := interface.io.isSoftReset
+
   downCDRIn.io.serDat  := io.dDatIn
   downCDRIn.io.overCLK := io.clk8x
 
diff --git a/tb/shinTest/ShinTopSpiTb.v b/tb/shinTest/ShinTopSpiTb.v
index 82d0423..d063b87 100644
--- a/tb/shinTest/ShinTopSpiTb.v
+++ b/tb/shinTest/ShinTopSpiTb.v
@@ -26,9 +26,11 @@ module ShinTopSpiTb(
     integer spidata_file;
     integer c_line;
 
+    wire [4:0] isSoftReset;
+
 ShinTop s_ShinTop_Mst(
   .clock(clock),
-  .reset(reset),
+  .reset(reset | isSoftReset[0]),
 
   .io_clk8x(clk8x),
   .io_dDatIn(1'b0),
@@ -55,13 +57,13 @@ ShinTop s_ShinTop_Mst(
   .io_oqspi_csn(spi_csn[10]),
 
   .io_rsp_valid(isResp),
-  .io_rsp_bits_isError()
-  // .io_rsp_bits_length()
+  .io_rsp_bits_isError(),
+  .io_isSoftReset(isSoftReset[0])
 );
 
 ShinTop s_ShinTop_slv0(
   .clock(clock),
-  .reset(reset),
+  .reset(reset | isSoftReset[1]),
 
   .io_clk8x(clk8x),
   .io_dDatIn(dDat_w[0]),
@@ -87,13 +89,13 @@ ShinTop s_ShinTop_slv0(
   .io_oqspi_csn(spi_csn[11]),
 
   .io_rsp_valid(),
-  .io_rsp_bits_isError()
-  // .io_rsp_bits_length()
+  .io_rsp_bits_isError(),
+  .io_isSoftReset(isSoftReset[1])
 );
 
 ShinTop s_ShinTop_slv1(
   .clock(clock),
-  .reset(reset),
+  .reset(reset | isSoftReset[2]),
 
   .io_clk8x(clk8x),
   .io_dDatIn(dDat_w[1]),
@@ -119,13 +121,13 @@ ShinTop s_ShinTop_slv1(
   .io_oqspi_csn(spi_csn[12]),
 
   .io_rsp_valid(),
-  .io_rsp_bits_isError()
-  // .io_rsp_bits_length()
+  .io_rsp_bits_isError(),
+  .io_isSoftReset(isSoftReset[2])
 );
 
 ShinTop s_ShinTop_slv2(
   .clock(clock),
-  .reset(reset),
+  .reset(reset | isSoftReset[3]),
 
   .io_clk8x(clk8x),
   .io_dDatIn(dDat_w[2]),
@@ -151,13 +153,13 @@ ShinTop s_ShinTop_slv2(
   .io_oqspi_csn(spi_csn[13]),
 
   .io_rsp_valid(),
-  .io_rsp_bits_isError()
-  // .io_rsp_bits_length()
+  .io_rsp_bits_isError(),
+  .io_isSoftReset(isSoftReset[3])
 );
 
 ShinTop s_ShinTop_slv3(
   .clock(clock),
-  .reset(reset),
+  .reset(reset | isSoftReset[4]),
 
   .io_clk8x(clk8x),
   .io_dDatIn(dDat_w[3]),
@@ -183,8 +185,8 @@ ShinTop s_ShinTop_slv3(
   .io_oqspi_csn(spi_csn[14]),
 
   .io_rsp_valid(),
-  .io_rsp_bits_isError()
-  // .io_rsp_bits_length()
+  .io_rsp_bits_isError(),
+  .io_isSoftReset(isSoftReset[4])
 );
 
 
@@ -766,6 +768,11 @@ initial begin
     txBuf[6+3] = 0;  //负载0x128 sync3脉冲宽度
     txBuf[7+3] = 0;  //负载0x129
     spi_trans( (16'h0122), (`SPI_WRITE), (8), (`IF_IDX(2)) ); //slv2
+
+  //复位系统
+    txBuf[0+3] = 8'h01;
+    spi_trans( (16'h40), (`SPI_WRITE), (1), (`IF_IDX(0)) );//复位主站
+    spi_trans( (16'h40), (`SPI_WRITE), (1), (`IF_IDX(3)) );//复位从站2
 end