调整中断,不使能也会改变状态

This commit is contained in:
Ruige Lee
2025-07-29 15:36:24 +08:00
parent 0ffa20bbfb
commit 72916a5420

View File

@@ -874,12 +874,12 @@ trait InterfaceSystem{ this: InterfaceBase =>
val intPulseWidth = cReg.intMode(14,0) val intPulseWidth = cReg.intMode(14,0)
//主站发送完成 //主站发送完成
when( io.intMstTrig(0) & cReg.intEnable(0) ){ when( io.intMstTrig(0) ){
intStatus(0) := true.B intStatus(0) := true.B
} }
//主站接收完成 //主站接收完成
when( io.intMstTrig(1) & cReg.intEnable(1) ){ when( io.intMstTrig(1) ){
intStatus(1) := true.B intStatus(1) := true.B
} }
@@ -887,7 +887,7 @@ trait InterfaceSystem{ this: InterfaceBase =>
//看门狗溢出 //看门狗溢出
when( io.wdtTrigger.reduce(_|_) & cReg.intEnable(4) ){ when( io.wdtTrigger.reduce(_|_) ){
intStatus(4) := true.B intStatus(4) := true.B
} }
@@ -896,7 +896,7 @@ trait InterfaceSystem{ this: InterfaceBase =>
//从站SM请求 //从站SM请求
for( i <- 0 until 8 ){ for( i <- 0 until 8 ){
when( io.intSlvTrig(i) & cReg.intEnable(8+i)){ when( io.intSlvTrig(i) ){
intStatus(8+i) := true.B intStatus(8+i) := true.B
} }
} }
@@ -937,7 +937,7 @@ trait InterfaceSystem{ this: InterfaceBase =>
(io.intMstTrig(0) & cReg.intEnable(0)) | //主站发送完成 (io.intMstTrig(0) & cReg.intEnable(0)) | //主站发送完成
(io.intMstTrig(1) & cReg.intEnable(1)) | //主站接收完成 (io.intMstTrig(1) & cReg.intEnable(1)) | //主站接收完成
false.B | //主站发送周期到了 false.B | //主站发送周期到了
false.B | //主站接收看门狗溢出 io.wdtTrigger.reduce(_|_) | //主站接收看门狗溢出
(0 until 8).map{ i => io.intSlvTrig(i) & cReg.intEnable(8+i)}.reduce(_|_) | //从站SM请求 (0 until 8).map{ i => io.intSlvTrig(i) & cReg.intEnable(8+i)}.reduce(_|_) | //从站SM请求
io.intHWTrig(0) | io.intHWTrig(1)//下行接收硬件错误 io.intHWTrig(0) | io.intHWTrig(1)//下行接收硬件错误
@@ -953,7 +953,7 @@ trait InterfaceSystem{ this: InterfaceBase =>
intPulseResetCnt := intPulseResetCnt + 1.U intPulseResetCnt := intPulseResetCnt + 1.U
} }
io.interrupt := Mux( isLevelInt, intStatus.reduce(_|_), intPulse) io.interrupt := Mux( isLevelInt, (cReg.intStatus & cReg.intEnable).orR, intPulse)
} }