From 72916a5420c0870dc133b9fdd3f265ead55abc49 Mon Sep 17 00:00:00 2001
From: Ruige Lee <wut.ruigeli@gmail.com>
Date: Tue, 29 Jul 2025 15:36:24 +0800
Subject: [PATCH] =?UTF-8?q?=E8=B0=83=E6=95=B4=E4=B8=AD=E6=96=AD=EF=BC=8C?=
 =?UTF-8?q?=E4=B8=8D=E4=BD=BF=E8=83=BD=E4=B9=9F=E4=BC=9A=E6=94=B9=E5=8F=98?=
 =?UTF-8?q?=E7=8A=B6=E6=80=81?=
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---
 src/main/scala/backBoard/shin/Interface.scala | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index bdbe97e..401a3ac 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -874,12 +874,12 @@ trait InterfaceSystem{ this: InterfaceBase =>
   val intPulseWidth = cReg.intMode(14,0)
 
   //主站发送完成
-  when( io.intMstTrig(0) & cReg.intEnable(0) ){
+  when( io.intMstTrig(0) ){
     intStatus(0) := true.B
   }
 
   //主站接收完成
-  when( io.intMstTrig(1) & cReg.intEnable(1) ){
+  when( io.intMstTrig(1) ){
     intStatus(1) := true.B
   }
 
@@ -887,7 +887,7 @@ trait InterfaceSystem{ this: InterfaceBase =>
 
 
   //看门狗溢出
-  when( io.wdtTrigger.reduce(_|_) & cReg.intEnable(4) ){
+  when( io.wdtTrigger.reduce(_|_) ){
     intStatus(4) := true.B
   }
 
@@ -896,7 +896,7 @@ trait InterfaceSystem{ this: InterfaceBase =>
 
   //从站SM请求
   for( i <- 0 until 8 ){
-    when( io.intSlvTrig(i) & cReg.intEnable(8+i)){
+    when( io.intSlvTrig(i) ){
       intStatus(8+i) := true.B
     }
   }
@@ -937,7 +937,7 @@ trait InterfaceSystem{ this: InterfaceBase =>
     (io.intMstTrig(0) & cReg.intEnable(0)) | //主站发送完成
     (io.intMstTrig(1) & cReg.intEnable(1)) | //主站接收完成
     false.B | //主站发送周期到了
-    false.B | //主站接收看门狗溢出
+    io.wdtTrigger.reduce(_|_) | //主站接收看门狗溢出
     (0 until 8).map{ i => io.intSlvTrig(i) & cReg.intEnable(8+i)}.reduce(_|_) | //从站SM请求
     io.intHWTrig(0) | io.intHWTrig(1)//下行接收硬件错误
 
@@ -953,7 +953,7 @@ trait InterfaceSystem{ this: InterfaceBase =>
     intPulseResetCnt := intPulseResetCnt + 1.U
   }
 
-  io.interrupt := Mux( isLevelInt, intStatus.reduce(_|_), intPulse)
+  io.interrupt := Mux( isLevelInt, (cReg.intStatus & cReg.intEnable).orR, intPulse)
   
 
 }