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约束只能使用4页，留下升级空间

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RuigeLee
2024-07-03 18:39:01 +08:00
parent 73bfd7e109
commit 71a489a1d0
1 changed files with 1 additions and 5 deletions
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6
src/main/scala/backBoard/SpiSlv.scala
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@@ -6,8 +6,6 @@ import chisel3.util._
trait BackBoardSpiSlv{ this: BackBoardSlvLocal => trait BackBoardSpiSlv{ this: BackBoardSlvLocal =>
def page: Int
val sck = Wire(Bool()) val sck = Wire(Bool())
val mosi = Wire(Bool()) val mosi = Wire(Bool())
val csn = Wire(Bool()) val csn = Wire(Bool())
@@ -38,7 +36,7 @@ trait BackBoardSpiSlv{ this: BackBoardSlvLocal =>
val exReg_100M = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(8.W)) } val exReg_100M = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(8.W)) }
val exMask_100M = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(16.W)) } val exMask_100M = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(16.W)) }
val cmd_100M = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(8.W)) } val cmd_100M = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(8.W)) }
val pageSel = cmd_100M(7,4) val pageSel = cmd_100M(5,4)
val spiCmd = cmd_100M(3,0) val spiCmd = cmd_100M(3,0)
val bitSel = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(3.W)) } val bitSel = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(3.W)) }
@@ -99,8 +97,6 @@ class SpiSlv extends BackBoardSlvLocal
with BackBoardSlvStatusPR with BackBoardSlvStatusPR
with BackBoardSpiSlv{ with BackBoardSpiSlv{
def page: Int = 1
val spi = IO(new Bundle{ val spi = IO(new Bundle{
val sck = Input(Bool()) val sck = Input(Bool())
val mosi = Input(Bool()) val mosi = Input(Bool())