diff --git a/src/main/scala/backBoard/SpiSlv.scala b/src/main/scala/backBoard/SpiSlv.scala
index dc5a1ff..903afc5 100644
--- a/src/main/scala/backBoard/SpiSlv.scala
+++ b/src/main/scala/backBoard/SpiSlv.scala
@@ -6,8 +6,6 @@ import chisel3.util._
 
 trait BackBoardSpiSlv{ this: BackBoardSlvLocal =>
 
-  def page: Int
-
   val sck = Wire(Bool())
   val mosi = Wire(Bool())
   val csn   = Wire(Bool())
@@ -38,7 +36,7 @@ trait BackBoardSpiSlv{ this: BackBoardSlvLocal =>
   val exReg_100M = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(8.W)) }
   val exMask_100M = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(16.W)) }
   val cmd_100M = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(8.W)) }
-  val pageSel = cmd_100M(7,4)
+  val pageSel = cmd_100M(5,4)
   val spiCmd  = cmd_100M(3,0)
 
   val bitSel  = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(3.W)) }
@@ -99,8 +97,6 @@ class SpiSlv extends BackBoardSlvLocal
 with BackBoardSlvStatusPR
 with BackBoardSpiSlv{
 
-  def page: Int = 1
-
   val spi = IO(new Bundle{
     val sck  = Input(Bool())
     val mosi = Input(Bool())