拓扑修改,编译通过

This commit is contained in:
RuigeLee
2023-10-19 15:24:26 +08:00
parent d77c69aa5a
commit 70922ecb44
22 changed files with 303 additions and 228 deletions

View File

@@ -0,0 +1,34 @@
package Switch
import chisel3._
import chisel3.stage._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config._
abstract class SwitchModule(implicit val p: Parameters) extends Module with HasSwitchParameters { def io: Record }
abstract class SwitchBundle(implicit val p: Parameters) extends Bundle with HasSwitchParameters
case object SwitchParamsKey extends Field[SwitchSetting]
case class SwitchSetting(
// isTileLink: Boolean = true
chn: Int = 1
){
}
trait HasSwitchParameters {
implicit val p: Parameters
val switchSetting = p(SwitchParamsKey)
def chn = switchSetting.chn
}
class SwitchCfg extends Config((_, _, _) => {
case SwitchParamsKey => SwitchSetting()
})