diff --git a/Makefile b/Makefile
index 333d9ba..72070c3 100644
--- a/Makefile
+++ b/Makefile
@@ -3,8 +3,14 @@
 
 compile:
 	rm -rf ./generated/
-	sbt "test:runMain test.testModule"
-
+	rm -rf ./rocket-chip/vsim/generated-src/
+	mkdir -p ./generated/
+	cd ./rocket-chip/ && rm -f rocketchip.jar
+	cd ./rocket-chip/vsim && make verilog CONFIG=freechips.rocketchip.system.UserFPGAConfig
+	cp ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.UserFPGAConfig.v ./generated/UserFPGAConfig.v
+	cp ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.UserFPGAConfig.behav_srams.v ./generated/behav_srams.v
+# 	sbt "test:runMain test.testModule"
+	
 
 
 VSimTop: 
diff --git a/src/main/scala/mac/MacRegisters.scala b/src/main/scala/Switch/MacRegisters.scala
similarity index 99%
rename from src/main/scala/mac/MacRegisters.scala
rename to src/main/scala/Switch/MacRegisters.scala
index 5e44a01..2a5bd3f 100644
--- a/src/main/scala/mac/MacRegisters.scala
+++ b/src/main/scala/Switch/MacRegisters.scala
@@ -9,8 +9,7 @@ import org.chipsalliance.cde.config._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.interrupts._
 
-class MacRegIO extends Bundle{
-
+class Mac_Config_Bundle extends Bundle{
   val WCtrlDataStart      = Input(Bool())
   val RStatStart          = Input(Bool())
   val UpdateMIIRX_DATAReg = Input(Bool())
@@ -68,10 +67,14 @@ class MacRegIO extends Bundle{
   val r_CtrlData  = Output(UInt(16.W))
   val r_MAC       = Output(UInt(48.W))
   val r_TxBDNum   = Output(UInt(8.W))
-  // val int_o       = Output(Bool())
   val r_TxPauseTV = Output(UInt(16.W))
   val r_TxPauseRq = Output(Bool())
+}
 
+
+
+
+class MacRegIO extends Mac_Config_Bundle{
   val asyncReset = Input(AsyncReset())
 }
 
diff --git a/src/main/scala/mac/MacRx.scala b/src/main/scala/Switch/MacRx.scala
similarity index 100%
rename from src/main/scala/mac/MacRx.scala
rename to src/main/scala/Switch/MacRx.scala
diff --git a/src/main/scala/mac/MacTx.scala b/src/main/scala/Switch/MacTx.scala
similarity index 100%
rename from src/main/scala/mac/MacTx.scala
rename to src/main/scala/Switch/MacTx.scala
diff --git a/src/main/scala/Switch/Parameters.scala b/src/main/scala/Switch/Parameters.scala
new file mode 100644
index 0000000..514d401
--- /dev/null
+++ b/src/main/scala/Switch/Parameters.scala
@@ -0,0 +1,34 @@
+package Switch
+
+import chisel3._
+import chisel3.stage._
+import freechips.rocketchip.diplomacy._
+
+import org.chipsalliance.cde.config._
+
+abstract class SwitchModule(implicit val p: Parameters) extends Module with HasSwitchParameters { def io: Record }
+abstract class SwitchBundle(implicit val p: Parameters) extends Bundle with HasSwitchParameters
+
+
+case object SwitchParamsKey extends Field[SwitchSetting]
+
+
+case class SwitchSetting(
+  // isTileLink: Boolean = true
+  chn: Int = 1
+){
+
+}
+
+trait HasSwitchParameters {
+  implicit val p: Parameters
+
+  val switchSetting = p(SwitchParamsKey)
+
+  def chn = switchSetting.chn
+
+}
+
+class SwitchCfg extends Config((_, _, _) => {
+  case SwitchParamsKey => SwitchSetting()
+})
diff --git a/src/main/scala/Switch/Switch.scala b/src/main/scala/Switch/Switch.scala
new file mode 100644
index 0000000..72f52c9
--- /dev/null
+++ b/src/main/scala/Switch/Switch.scala
@@ -0,0 +1,81 @@
+package Switch
+
+import chisel3._
+import chisel3.util._
+
+import MAC._
+
+import org.chipsalliance.cde.config._
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.interrupts._
+
+import chisel3.experimental.dataview._
+
+
+class SwitchIO(implicit p: Parameters) extends SwitchBundle{
+  val mii = Vec( chn, new MII )
+
+  val isLoopBack = Output(Vec( chn, Bool()))
+  val asyncReset = Input(AsyncReset())
+}
+
+
+class Switch(implicit p: Parameters) extends LazyModule with HasSwitchParameters{
+
+
+  val ethReg = LazyModule(new MacReg)
+
+  lazy val module = new SwitchImp(this)
+
+}
+
+class SwitchImp(outer: Switch)(implicit p: Parameters) extends LazyModuleImp(outer) with HasSwitchParameters{
+  val io = IO(new SwitchIO)
+
+  val mac = ( 0 until chn ).map{ i =>
+    Module(new Mac)
+  }
+
+  ( 0 until chn ).map{ i =>
+    mac(i).io.mii <> io.mii(i)
+    mac(i).io.asyncReset := io.asyncReset
+    io.isLoopBack(i) := mac(i).io.isLoopBack
+  }
+
+  outer.ethReg.module.io.asyncReset := io.asyncReset
+  outer.ethReg.module.io.viewAsSupertype(new Mac_Config_Bundle) <> mac(0).io.cfg
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  val rxBuff = Module(new RxBuff)
+
+  rxBuff.io.enq <> mac(0).io.rxEnq
+  rxBuff.io.deq.data.ready := false.B
+  rxBuff.io.deq.ctrl.ready := false.B
+
+  val txBuff = Module(new TxBuff)
+  txBuff.io.deq <> mac(0).io.txDeq
+  txBuff.io.enq.ctrl.valid := false.B
+  txBuff.io.enq.data.valid := false.B
+  txBuff.io.enq.data.bits  := 0.U
+
+
+
+
+}
+
diff --git a/src/main/scala/Switch/WithSwitch.scala b/src/main/scala/Switch/WithSwitch.scala
new file mode 100644
index 0000000..7075453
--- /dev/null
+++ b/src/main/scala/Switch/WithSwitch.scala
@@ -0,0 +1,43 @@
+package Switch
+
+import chisel3._
+
+import freechips.rocketchip.subsystem.BaseSubsystem
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.tilelink._
+import org.chipsalliance.cde.config._
+
+
+trait WithSwitchMix { this: BaseSubsystem =>
+
+    val switch = LazyModule(new Switch)
+
+    // sbus.coupleFrom("switch_mst") { _ := TLBuffer() := switch0.tlClientNode }
+    // pbus.coupleTo("switch_cfg")   { switch0.tlMasterNode := TLFragmenter(pbus) := _ }
+    pbus.coupleTo("switch_cfg")   { switch.ethReg.configNode   := TLFragmenter(pbus) := _ }
+
+    ibus.fromSync := switch.ethReg.int_node
+
+}
+
+
+trait WithSwitchMixModuleImp extends LazyModuleImp {
+  val outer: WithSwitchMix
+
+  val switchIO = IO(new SwitchIO)
+
+  switchIO <> outer.switch.module.io
+
+  println("Warning, did you delete the rocket-chip.jar on top to reflash?")
+  println("Warning, did you delete the rocket-chip.jar on top to reflash?")
+  println("Warning, did you delete the rocket-chip.jar on top to reflash?")
+  println("Warning, did you delete the rocket-chip.jar on top to reflash?")
+  println("Warning, did you delete the rocket-chip.jar on top to reflash?")
+
+}
+
+class SwitchConfig() extends Config((site, here, up) => {
+  case SwitchParamsKey => SwitchSetting()
+})
+
+
diff --git a/src/main/scala/mac/AsyncFifo.scala.bk b/src/main/scala/Switch/mac/AsyncFifo.scala.bk
similarity index 100%
rename from src/main/scala/mac/AsyncFifo.scala.bk
rename to src/main/scala/Switch/mac/AsyncFifo.scala.bk
diff --git a/src/main/scala/mac/MAC.scala b/src/main/scala/Switch/mac/MAC.scala
similarity index 82%
rename from src/main/scala/mac/MAC.scala
rename to src/main/scala/Switch/mac/MAC.scala
index 8d49dd5..06d6574 100644
--- a/src/main/scala/mac/MAC.scala
+++ b/src/main/scala/Switch/mac/MAC.scala
@@ -3,28 +3,11 @@ package MAC
 import chisel3._
 import chisel3.util._
 
-import org.chipsalliance.cde.config._
-import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.tilelink._
-import freechips.rocketchip.interrupts._
-
-class Mac(implicit p: Parameters) extends LazyModule with HasMacParameters{
-
-
-  val ethReg = LazyModule(new MacReg)
-
-
-  lazy val module = new MacImp(this)
+import Switch._
 
 
 
-
-}
-
-
-
-class MacIO extends Bundle with MDIO{
-
+class MII extends Bundle with MDIO{
   // Tx
   val mtx_clk_pad_i = Input(Bool())
   val mtxd_pad_o    = Output(UInt(4.W))
@@ -39,7 +22,16 @@ class MacIO extends Bundle with MDIO{
 
   // Common Tx and Rx
   val mcoll_pad_i = Input(Bool())
-  val mcrs_pad_i  = Input(Bool())
+  val mcrs_pad_i  = Input(Bool())  
+}
+
+
+
+class MacIO extends Bundle{
+  val mii = new MII
+  val cfg = Flipped(new Mac_Config_Bundle)
+  val rxEnq = new Receive_Enq_Bundle
+  val txDeq = Flipped(new Transmit_Deq_Bundle)
 
   // val int_o = Output(Bool())
 
@@ -47,7 +39,8 @@ class MacIO extends Bundle with MDIO{
   val asyncReset = Input(AsyncReset())
 }
 
-class MacImp(outer: Mac)(implicit p: Parameters) extends LazyModuleImp(outer) with HasMacParameters{
+
+class Mac extends Module{
 
   val io = IO(new MacIO)
 
@@ -124,7 +117,7 @@ val miim = Module(new MIIM)
   miim.io.RStat     := r_RStat
   miim.io.ScanStat  := r_ScanStat
 
-  miim.io.mdi   := io.mdi
+  miim.io.mdi   := io.mii.mdi
 
   Busy_stat := miim.io.Busy
   LinkFail  := miim.io.LinkFail
@@ -134,9 +127,9 @@ val miim = Module(new MIIM)
   RStatStart := miim.io.RStatStart
   UpdateMIIRX_DATAReg := miim.io.UpdateMIIRX_DATAReg
 
-  io.mdc   := miim.io.mdc
-  io.mdo   := miim.io.mdo
-  io.mdoEn := miim.io.mdoEn
+  io.mii.mdc   := miim.io.mdc
+  io.mii.mdo   := miim.io.mdo
+  io.mii.mdoEn := miim.io.mdoEn
   
 
 
@@ -288,69 +281,65 @@ dontTouch(CarrierSenseLost           )
 
 
 
-
-outer.ethReg.module.io.asyncReset          := io.asyncReset
-outer.ethReg.module.io.WCtrlDataStart      := WCtrlDataStart
-outer.ethReg.module.io.RStatStart          := RStatStart
-outer.ethReg.module.io.UpdateMIIRX_DATAReg := UpdateMIIRX_DATAReg
-outer.ethReg.module.io.Prsd                := Prsd
-outer.ethReg.module.io.NValid_stat         := NValid_stat
-outer.ethReg.module.io.Busy_stat           := Busy_stat
-outer.ethReg.module.io.LinkFail            := LinkFail
-outer.ethReg.module.io.TxB_IRQ             := TxB_IRQ
-outer.ethReg.module.io.TxE_IRQ             := TxE_IRQ
-outer.ethReg.module.io.RxB_IRQ             := RxB_IRQ
-outer.ethReg.module.io.RxE_IRQ             := RxE_IRQ
-outer.ethReg.module.io.Busy_IRQ            := Busy_IRQ
-outer.ethReg.module.io.RstTxPauseRq        := RstTxPauseRq
-outer.ethReg.module.io.TxCtrlEndFrm        := TxCtrlEndFrm
-outer.ethReg.module.io.StartTxDone         := StartTxDone
-outer.ethReg.module.io.TxClk               := io.mtx_clk_pad_i
-outer.ethReg.module.io.RxClk               := io.mrx_clk_pad_i
-outer.ethReg.module.io.SetPauseTimer       := SetPauseTimer
+io.cfg.WCtrlDataStart      := WCtrlDataStart
+io.cfg.RStatStart          := RStatStart
+io.cfg.UpdateMIIRX_DATAReg := UpdateMIIRX_DATAReg
+io.cfg.Prsd                := Prsd
+io.cfg.NValid_stat         := NValid_stat
+io.cfg.Busy_stat           := Busy_stat
+io.cfg.LinkFail            := LinkFail
+io.cfg.TxB_IRQ             := TxB_IRQ
+io.cfg.TxE_IRQ             := TxE_IRQ
+io.cfg.RxB_IRQ             := RxB_IRQ
+io.cfg.RxE_IRQ             := RxE_IRQ
+io.cfg.Busy_IRQ            := Busy_IRQ
+io.cfg.RstTxPauseRq        := RstTxPauseRq
+io.cfg.TxCtrlEndFrm        := TxCtrlEndFrm
+io.cfg.StartTxDone         := StartTxDone
+io.cfg.TxClk               := io.mii.mtx_clk_pad_i
+io.cfg.RxClk               := io.mii.mrx_clk_pad_i
+io.cfg.SetPauseTimer       := SetPauseTimer
 
 
-r_RecSmall  := outer.ethReg.module.io.r_RecSmall
-r_Pad       := outer.ethReg.module.io.r_Pad
-r_HugEn     := outer.ethReg.module.io.r_HugEn
-r_CrcEn     := outer.ethReg.module.io.r_CrcEn
-r_DlyCrcEn  := outer.ethReg.module.io.r_DlyCrcEn
-r_FullD     := outer.ethReg.module.io.r_FullD
-r_ExDfrEn   := outer.ethReg.module.io.r_ExDfrEn
-r_NoBckof   := outer.ethReg.module.io.r_NoBckof
-r_LoopBck   := outer.ethReg.module.io.r_LoopBck
-r_IFG       := outer.ethReg.module.io.r_IFG
-r_Pro       := outer.ethReg.module.io.r_Pro
-r_Bro       := outer.ethReg.module.io.r_Bro
-r_NoPre     := outer.ethReg.module.io.r_NoPre
-r_TxEn      := outer.ethReg.module.io.r_TxEn
-r_RxEn      := outer.ethReg.module.io.r_RxEn
-r_HASH0     := outer.ethReg.module.io.r_HASH0
-r_HASH1     := outer.ethReg.module.io.r_HASH1
-r_IPGT      := outer.ethReg.module.io.r_IPGT
-r_IPGR1     := outer.ethReg.module.io.r_IPGR1
-r_IPGR2     := outer.ethReg.module.io.r_IPGR2
-r_MinFL     := outer.ethReg.module.io.r_MinFL
-r_MaxFL     := outer.ethReg.module.io.r_MaxFL
-r_MaxRet    := outer.ethReg.module.io.r_MaxRet
-r_CollValid := outer.ethReg.module.io.r_CollValid
-r_TxFlow    := outer.ethReg.module.io.r_TxFlow
-r_RxFlow    := outer.ethReg.module.io.r_RxFlow
-r_PassAll   := outer.ethReg.module.io.r_PassAll
-r_MiiNoPre  := outer.ethReg.module.io.r_MiiNoPre
-r_ClkDiv    := outer.ethReg.module.io.r_ClkDiv
-r_WCtrlData := outer.ethReg.module.io.r_WCtrlData
-r_RStat     := outer.ethReg.module.io.r_RStat
-r_ScanStat  := outer.ethReg.module.io.r_ScanStat
-r_RGAD      := outer.ethReg.module.io.r_RGAD
-r_FIAD      := outer.ethReg.module.io.r_FIAD
-r_CtrlData  := outer.ethReg.module.io.r_CtrlData
-r_MAC       := outer.ethReg.module.io.r_MAC
-r_TxBDNum   := outer.ethReg.module.io.r_TxBDNum
-// io.int_o    := outer.ethReg.module.io.int_o
-  // int(0)    := outer.ethReg.module.io.int_o
-r_TxPauseTV := outer.ethReg.module.io.r_TxPauseTV
-r_TxPauseRq := outer.ethReg.module.io.r_TxPauseRq
+r_RecSmall  := io.cfg.r_RecSmall
+r_Pad       := io.cfg.r_Pad
+r_HugEn     := io.cfg.r_HugEn
+r_CrcEn     := io.cfg.r_CrcEn
+r_DlyCrcEn  := io.cfg.r_DlyCrcEn
+r_FullD     := io.cfg.r_FullD
+r_ExDfrEn   := io.cfg.r_ExDfrEn
+r_NoBckof   := io.cfg.r_NoBckof
+r_LoopBck   := io.cfg.r_LoopBck
+r_IFG       := io.cfg.r_IFG
+r_Pro       := io.cfg.r_Pro
+r_Bro       := io.cfg.r_Bro
+r_NoPre     := io.cfg.r_NoPre
+r_TxEn      := io.cfg.r_TxEn
+r_RxEn      := io.cfg.r_RxEn
+r_HASH0     := io.cfg.r_HASH0
+r_HASH1     := io.cfg.r_HASH1
+r_IPGT      := io.cfg.r_IPGT
+r_IPGR1     := io.cfg.r_IPGR1
+r_IPGR2     := io.cfg.r_IPGR2
+r_MinFL     := io.cfg.r_MinFL
+r_MaxFL     := io.cfg.r_MaxFL
+r_MaxRet    := io.cfg.r_MaxRet
+r_CollValid := io.cfg.r_CollValid
+r_TxFlow    := io.cfg.r_TxFlow
+r_RxFlow    := io.cfg.r_RxFlow
+r_PassAll   := io.cfg.r_PassAll
+r_MiiNoPre  := io.cfg.r_MiiNoPre
+r_ClkDiv    := io.cfg.r_ClkDiv
+r_WCtrlData := io.cfg.r_WCtrlData
+r_RStat     := io.cfg.r_RStat
+r_ScanStat  := io.cfg.r_ScanStat
+r_RGAD      := io.cfg.r_RGAD
+r_FIAD      := io.cfg.r_FIAD
+r_CtrlData  := io.cfg.r_CtrlData
+r_MAC       := io.cfg.r_MAC
+r_TxBDNum   := io.cfg.r_TxBDNum
+r_TxPauseTV := io.cfg.r_TxPauseTV
+r_TxPauseRq := io.cfg.r_TxPauseRq
 
 
 
@@ -405,8 +394,8 @@ dontTouch(StateData           )
 // Connecting MACControl
 val maccontrol = Module(new MacControl)
 
-maccontrol.io.MTxClk                     := io.mtx_clk_pad_i
-maccontrol.io.MRxClk                     := io.mrx_clk_pad_i
+maccontrol.io.MTxClk                     := io.mii.mtx_clk_pad_i
+maccontrol.io.MRxClk                     := io.mii.mrx_clk_pad_i
 maccontrol.io.asyncReset                 := io.asyncReset
 
 maccontrol.io.TPauseRq                   := TPauseRq
@@ -466,16 +455,16 @@ dontTouch(RxEnSync        )
 io.isLoopBack := r_LoopBck
 
 // Muxed MII receive data valid
-MRxDV_Lb := Mux(r_LoopBck, io.mtxen_pad_o, io.mrxdv_pad_i & RxEnSync)
+MRxDV_Lb := Mux(r_LoopBck, io.mii.mtxen_pad_o, io.mii.mrxdv_pad_i & RxEnSync)
 
 // Muxed MII Receive Error
-MRxErr_Lb := Mux(r_LoopBck, io.mtxerr_pad_o, io.mrxerr_pad_i & RxEnSync)
+MRxErr_Lb := Mux(r_LoopBck, io.mii.mtxerr_pad_o, io.mii.mrxerr_pad_i & RxEnSync)
 
 // Muxed MII Receive Data
-MRxD_Lb := Mux(r_LoopBck, io.mtxd_pad_o, io.mrxd_pad_i)
+MRxD_Lb := Mux(r_LoopBck, io.mii.mtxd_pad_o, io.mii.mrxd_pad_i)
 
 
-val txethmac = withClockAndReset(io.mtx_clk_pad_i.asClock, io.asyncReset)( Module(new MacTx))
+val txethmac = withClockAndReset(io.mii.mtx_clk_pad_i.asClock, io.asyncReset)( Module(new MacTx))
 
 txethmac.io.TxStartFrm      := TxStartFrmOut
 txethmac.io.TxEndFrm        := TxEndFrmOut
@@ -497,9 +486,9 @@ txethmac.io.MaxRet          := r_MaxRet
 txethmac.io.NoBckof         := r_NoBckof
 txethmac.io.ExDfrEn         := r_ExDfrEn
 
-io.mtxd_pad_o    := txethmac.io.MTxD
-io.mtxen_pad_o   := txethmac.io.MTxEn
-io.mtxerr_pad_o := txethmac.io.MTxErr
+io.mii.mtxd_pad_o    := txethmac.io.MTxD
+io.mii.mtxen_pad_o   := txethmac.io.MTxEn
+io.mii.mtxerr_pad_o := txethmac.io.MTxErr
 TxDoneIn := txethmac.io.TxDone
 TxRetry := txethmac.io.TxRetry
 TxAbortIn := txethmac.io.TxAbort
@@ -542,7 +531,7 @@ dontTouch(RxStateSFD       )
 dontTouch(RxStateData      )
 dontTouch(AddressMiss      )
 
-val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Module(new MacRx))
+val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( Module(new MacRx))
 
   rxethmac.io.MRxDV               := MRxDV_Lb
   rxethmac.io.MRxD                := MRxD_Lb
@@ -576,13 +565,13 @@ val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Modul
   AddressMiss       := rxethmac.io.AddressMiss
 
 
-  withClockAndReset( io.mtx_clk_pad_i.asClock, reset.asAsyncReset ) {
+  withClockAndReset( io.mii.mtx_clk_pad_i.asClock, reset.asAsyncReset ) {
     // MII Carrier Sense Synchronization
-    CarrierSense_Tx2 := ShiftRegister(io.mcrs_pad_i, 2, false.B, true.B)
+    CarrierSense_Tx2 := ShiftRegister(io.mii.mcrs_pad_i, 2, false.B, true.B)
 
     TxCarrierSense := ~r_FullD & CarrierSense_Tx2
 
-    val Collision_Tx1 = RegNext(io.mcoll_pad_i, false.B)
+    val Collision_Tx1 = RegNext(io.mii.mcoll_pad_i, false.B)
     val Collision_Tx2 = RegInit(false.B)
 
     when(ResetCollision){
@@ -600,11 +589,11 @@ val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Modul
 
 
 
-  withClockAndReset( io.mrx_clk_pad_i.asClock, reset.asAsyncReset ) {
+  withClockAndReset( io.mii.mrx_clk_pad_i.asClock, reset.asAsyncReset ) {
     val WillTransmit_q = ShiftRegister(WillTransmit, 2, false.B, true.B)
 
     Transmitting := ~r_FullD & WillTransmit_q
-    RxEnSync := RegEnable( ShiftRegister(r_RxEn, 2), false.B, ~io.mrxdv_pad_i)
+    RxEnSync := RegEnable( ShiftRegister(r_RxEn, 2), false.B, ~io.mii.mrxdv_pad_i)
   }
 
 
@@ -618,7 +607,7 @@ val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Modul
   }
 
 
-  withClockAndReset( io.mtx_clk_pad_i.asClock, reset.asAsyncReset ) {
+  withClockAndReset( io.mii.mtx_clk_pad_i.asClock, reset.asAsyncReset ) {
     val TxPauseRq_sync = ShiftRegisters((r_TxPauseRq & r_TxFlow), 3, false.B, true.B )
 
     TPauseRq := RegNext( TxPauseRq_sync(1) & (~TxPauseRq_sync(2)), false.B )
@@ -632,7 +621,7 @@ val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Modul
   val RxAbort_latch_wire = Wire(Bool())
   val RxAbort_wb = ShiftRegister( RxAbort_latch_wire, 2, false.B, true.B )
 
-  withClockAndReset( io.mrx_clk_pad_i.asClock, reset.asAsyncReset ) {
+  withClockAndReset( io.mii.mrx_clk_pad_i.asClock, reset.asAsyncReset ) {
     val RxAbort_latch = RegInit(false.B); RxAbort_latch_wire := RxAbort_latch
     val RxAbortRst = ShiftRegister( RxAbort_wb, 2, false.B, true.B )
     
@@ -673,7 +662,7 @@ val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Modul
   val macstatus = Module(new MacStatus)
 
   macstatus.io.asyncReset          := io.asyncReset
-  macstatus.io.MRxClk              := io.mrx_clk_pad_i
+  macstatus.io.MRxClk              := io.mii.mrx_clk_pad_i
   macstatus.io.RxCrcError          := RxCrcError
   macstatus.io.MRxErr              := MRxErr_Lb
   macstatus.io.MRxDV               := MRxDV_Lb
@@ -687,7 +676,7 @@ val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Modul
   macstatus.io.RxByteCntGreat2     := RxByteCntGreat2
   macstatus.io.RxByteCntMaxFrame   := RxByteCntMaxFrame
   macstatus.io.MRxD                := MRxD_Lb
-  macstatus.io.Collision           := io.mcoll_pad_i
+  macstatus.io.Collision           := io.mii.mcoll_pad_i
   macstatus.io.CollValid           := r_CollValid
   macstatus.io.r_RecSmall          := r_RecSmall
   macstatus.io.r_MinFL             := r_MinFL
@@ -696,7 +685,7 @@ val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Modul
   macstatus.io.StartTxDone         := StartTxDone
   macstatus.io.StartTxAbort        := StartTxAbort
   macstatus.io.RetryCnt            := RetryCnt
-  macstatus.io.MTxClk              := io.mtx_clk_pad_i
+  macstatus.io.MTxClk              := io.mii.mtx_clk_pad_i
   macstatus.io.MaxCollisionOccured := MaxCollisionOccured
   macstatus.io.LateCollision       := LateCollision
   macstatus.io.DeferIndication     := DeferIndication
@@ -745,13 +734,13 @@ val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Modul
 
 
 
-  val macTileLinkTx = withClockAndReset( io.mtx_clk_pad_i.asClock, io.asyncReset ) (Module(new MacTileLinkTx))
+  val macTileLinkTx = withClockAndReset( io.mii.mtx_clk_pad_i.asClock, io.asyncReset ) (Module(new MacTileLinkTx))
 
   // Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
   val ReadTxDataFromFifo_sync = ShiftRegister( macTileLinkTx.io.ReadTxDataFromFifo_tck, 2, false.B, true.B)
   wishbone.io.ReadTxDataFromFifo_sync := ReadTxDataFromFifo_sync
 
-  withClockAndReset( io.mtx_clk_pad_i.asClock, io.asyncReset ){
+  withClockAndReset( io.mii.mtx_clk_pad_i.asClock, io.asyncReset ){
     macTileLinkTx.io.BlockingTxStatusWrite_sync := ShiftRegister( wishbone.io.BlockingTxStatusWrite, 2, false.B, true.B)
     macTileLinkTx.io.TxStartFrm_sync            := ShiftRegister( wishbone.io.TxStartFrm_wb, 2, false.B, true.B ) // Synchronizing TxStartFrm_wb to MTxClk
     macTileLinkTx.io.ReadTxDataFromFifo_syncb   := ShiftRegister( ReadTxDataFromFifo_sync, 2, false.B, true.B)    
@@ -802,7 +791,7 @@ val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Modul
 
 
 
-  val macTileLinkRx = withClockAndReset( io.mrx_clk_pad_i.asClock, io.asyncReset ) ( Module(new MacTileLinkRx) )
+  val macTileLinkRx = withClockAndReset( io.mii.mrx_clk_pad_i.asClock, io.asyncReset ) ( Module(new MacTileLinkRx) )
 
 
 
@@ -830,7 +819,7 @@ val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Modul
   val Busy_IRQ_sync = ShiftRegister(macTileLinkRx.io.Busy_IRQ_rck, 2, false.B, true.B)
   Busy_IRQ := Busy_IRQ_sync & ~RegNext(Busy_IRQ_sync, false.B)
 
-  withClockAndReset( io.mrx_clk_pad_i.asClock, io.asyncReset ) {
+  withClockAndReset( io.mii.mrx_clk_pad_i.asClock, io.asyncReset ) {
     val ShiftEndedSyncb = ShiftRegister( ShiftEndedSync, 2, false.B, true.B)
     RxStatusWriteLatchedSync         := ShiftEndedSyncb 
     macTileLinkRx.io.ShiftEndedSyncb := ShiftEndedSyncb 
@@ -854,12 +843,8 @@ val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Modul
   macTileLinkRx.io.RxStatusIn   := Cat(ReceivedPauseFrm, AddressMiss, false.B, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision)
 
 
-
-
-
-
-
-
+  wishbone.io.rxEnq <> io.rxEnq
+  wishbone.io.txDeq <> io.txDeq
 }
 
 
diff --git a/src/main/scala/mac/MII.scala b/src/main/scala/Switch/mac/MII.scala
similarity index 100%
rename from src/main/scala/mac/MII.scala
rename to src/main/scala/Switch/mac/MII.scala
diff --git a/src/main/scala/mac/MacBundle.scala b/src/main/scala/Switch/mac/MacBundle.scala
similarity index 100%
rename from src/main/scala/mac/MacBundle.scala
rename to src/main/scala/Switch/mac/MacBundle.scala
diff --git a/src/main/scala/mac/MacControl.scala b/src/main/scala/Switch/mac/MacControl.scala
similarity index 100%
rename from src/main/scala/mac/MacControl.scala
rename to src/main/scala/Switch/mac/MacControl.scala
diff --git a/src/main/scala/mac/MacFifo.scala b/src/main/scala/Switch/mac/MacFifo.scala
similarity index 100%
rename from src/main/scala/mac/MacFifo.scala
rename to src/main/scala/Switch/mac/MacFifo.scala
diff --git a/src/main/scala/mac/MacSRAM.scala b/src/main/scala/Switch/mac/MacSRAM.scala
similarity index 100%
rename from src/main/scala/mac/MacSRAM.scala
rename to src/main/scala/Switch/mac/MacSRAM.scala
diff --git a/src/main/scala/mac/MacStatus.scala b/src/main/scala/Switch/mac/MacStatus.scala
similarity index 100%
rename from src/main/scala/mac/MacStatus.scala
rename to src/main/scala/Switch/mac/MacStatus.scala
diff --git a/src/main/scala/mac/MacTileLinkRx.scala b/src/main/scala/Switch/mac/MacTileLinkRx.scala
similarity index 100%
rename from src/main/scala/mac/MacTileLinkRx.scala
rename to src/main/scala/Switch/mac/MacTileLinkRx.scala
diff --git a/src/main/scala/mac/MacTileLinkTx.scala b/src/main/scala/Switch/mac/MacTileLinkTx.scala
similarity index 100%
rename from src/main/scala/mac/MacTileLinkTx.scala
rename to src/main/scala/Switch/mac/MacTileLinkTx.scala
diff --git a/src/main/scala/mac/MacTilelink.scala b/src/main/scala/Switch/mac/MacTilelink.scala
similarity index 73%
rename from src/main/scala/mac/MacTilelink.scala
rename to src/main/scala/Switch/mac/MacTilelink.scala
index 19d0063..49aaf33 100644
--- a/src/main/scala/mac/MacTilelink.scala
+++ b/src/main/scala/Switch/mac/MacTilelink.scala
@@ -56,7 +56,8 @@ abstract class MacTileLinkBase() extends Module{
     val TxDoneSync  = Input(Bool())      // Transmission ended
 
 
-
+    val rxEnq = new Receive_Enq_Bundle
+    val txDeq = Flipped(new Transmit_Deq_Bundle)
 
   }
 
@@ -64,8 +65,8 @@ abstract class MacTileLinkBase() extends Module{
   
   val io = IO(new MacTileLinkIO)
 
-  val txBuff = Module(new TxBuff)
-  val rxBuff = Module(new RxBuff)
+
+
 
   val ShiftEndedSyncPluse         = io.ShiftEndedSync          & ~RegNext(io.ShiftEndedSync, false.B)
   val RxAbortPluse                = io.RxAbortSync             & ~RegNext(io.RxAbortSync, false.B)
@@ -75,12 +76,12 @@ abstract class MacTileLinkBase() extends Module{
 
 
   val rxBuffCtrlValid = RegInit(false.B)
-  rxBuff.io.enq.ctrl.valid := rxBuffCtrlValid
-  rxBuff.io.enq.ctrl.bits.LatchedRxLength   := RegEnable(io.LatchedRxLength_rxclk,   ShiftEndedSyncPluse | RxAbortPluse)
-  rxBuff.io.enq.ctrl.bits.RxStatusInLatched := RegEnable(io.RxStatusInLatched_rxclk, ShiftEndedSyncPluse | RxAbortPluse)
-  rxBuff.io.enq.ctrl.bits.isRxAbort         := RegEnable(RxAbortPluse,      false.B, ShiftEndedSyncPluse | RxAbortPluse)
+  io.rxEnq.ctrl.valid := rxBuffCtrlValid
+  io.rxEnq.ctrl.bits.LatchedRxLength   := RegEnable(io.LatchedRxLength_rxclk,   ShiftEndedSyncPluse | RxAbortPluse)
+  io.rxEnq.ctrl.bits.RxStatusInLatched := RegEnable(io.RxStatusInLatched_rxclk, ShiftEndedSyncPluse | RxAbortPluse)
+  io.rxEnq.ctrl.bits.isRxAbort         := RegEnable(RxAbortPluse,      false.B, ShiftEndedSyncPluse | RxAbortPluse)
 
-  when( rxBuff.io.enq.ctrl.fire ){
+  when( io.rxEnq.ctrl.fire ){
     rxBuffCtrlValid := false.B
   } .elsewhen( ShiftEndedSyncPluse | RxAbortPluse ){
     rxBuffCtrlValid := true.B
@@ -91,15 +92,15 @@ abstract class MacTileLinkBase() extends Module{
   // RxReady generation
   when(ShiftEndedSyncPluse | RxAbortPluse  ){
     RxReady := false.B
-  } .elsewhen( io.r_RxEn & (rxBuff.io.enq.data.ready) ){
+  } .elsewhen( io.r_RxEn & (io.rxEnq.data.ready) ){
     RxReady := true.B
   }
 
 
-  rxBuff.io.enq.data.bits := io.RxDataLatched2_rxclk
-  rxBuff.io.enq.data.valid := WriteRxDataToFifoSyncPluse 
+  io.rxEnq.data.bits := io.RxDataLatched2_rxclk
+  io.rxEnq.data.valid := WriteRxDataToFifoSyncPluse 
 
-  assert( ~(rxBuff.io.enq.data.valid & ~rxBuff.io.enq.data.ready), "Assert Failed, rx overrun!" )
+  assert( ~(io.rxEnq.data.valid & ~io.rxEnq.data.ready), "Assert Failed, rx overrun!" )
 
 
 
@@ -133,10 +134,10 @@ abstract class MacTileLinkBase() extends Module{
   val ReadTxDataFromFifoSyncPluse = io.ReadTxDataFromFifo_sync & ~RegNext(io.ReadTxDataFromFifo_sync, false.B)
 
   
-  io.PerPacketPad    := RegEnable(txBuff.io.deq.req.bits.PerPacketPad, false.B, txBuff.io.deq.req.fire)
-  io.PerPacketCrcEn  := RegEnable(txBuff.io.deq.req.bits.PerPacketCrcEn, false.B, txBuff.io.deq.req.fire)
+  io.PerPacketPad    := RegEnable(io.txDeq.req.bits.PerPacketPad,   false.B, io.txDeq.req.fire)
+  io.PerPacketCrcEn  := RegEnable(io.txDeq.req.bits.PerPacketCrcEn, false.B, io.txDeq.req.fire)
 
-  when( txBuff.io.deq.req.fire ){
+  when( io.txDeq.req.fire ){
     TxStartFrm_wb := true.B
   } .elsewhen(io.TxStartFrm_syncb){
     TxStartFrm_wb := false.B
@@ -149,11 +150,11 @@ abstract class MacTileLinkBase() extends Module{
     TxEndFrm_wb := false.B
   }
 
-  when( txBuff.io.deq.req.fire ){
+  when( io.txDeq.req.fire ){
 
-    TxLength        := txBuff.io.deq.req.bits.txLength
-    LatchedTxLength := txBuff.io.deq.req.bits.txLength
-  } .elsewhen( txBuff.io.deq.data.fire ){
+    TxLength        := io.txDeq.req.bits.txLength
+    LatchedTxLength := io.txDeq.req.bits.txLength
+  } .elsewhen( io.txDeq.data.fire ){
     when( TxLength < 4.U ){
       TxLength := 0.U
     } .otherwise{
@@ -165,10 +166,10 @@ abstract class MacTileLinkBase() extends Module{
   val txRespValid = RegInit(false.B)
   val txRespBits  = Reg(new Transmit_Deq_Resp_Bundle)
 
-  txBuff.io.deq.resp.valid := txRespValid
-  txBuff.io.deq.resp.bits  := txRespBits
+  io.txDeq.resp.valid := txRespValid
+  io.txDeq.resp.bits  := txRespBits
 
-  when( txBuff.io.deq.resp.fire ){
+  when( io.txDeq.resp.fire ){
     txRespValid := false.B
   } .elsewhen( txRetryPulse | txDonePulse | txAbortPulse ){
     txRespValid := true.B
@@ -185,9 +186,9 @@ abstract class MacTileLinkBase() extends Module{
 
 
 
-  val isTxBusy = RegInit(false.B); txBuff.io.deq.req.ready := ~isTxBusy & io.r_TxEn
+  val isTxBusy = RegInit(false.B); io.txDeq.req.ready := ~isTxBusy & io.r_TxEn
 
-  when(txBuff.io.deq.req.fire){
+  when( io.txDeq.req.fire){
     isTxBusy := true.B
   } .elsewhen(txRetryPulse | txDonePulse | txAbortPulse){
     isTxBusy := false.B
@@ -199,10 +200,10 @@ abstract class MacTileLinkBase() extends Module{
 
 
 
-  txBuff.io.deq.data.ready    := ReadTxDataFromFifoSyncPluse
-  assert( ~(txBuff.io.deq.data.ready & ~txBuff.io.deq.data.valid), "Assert Failed, Tx should never under run!" )
+  io.txDeq.data.ready    := ReadTxDataFromFifoSyncPluse
+  assert( ~(io.txDeq.data.ready & ~io.txDeq.data.valid), "Assert Failed, Tx should never under run!" )
 
-  io.TxData_wb       := txBuff.io.deq.data.bits
+  io.TxData_wb       := io.txDeq.data.bits
 
 
 
@@ -252,12 +253,9 @@ abstract class MacTileLinkBase() extends Module{
 
 
 class MacTileLink() extends MacTileLinkBase(){
-  txBuff.io.enq.ctrl.valid := false.B
-  txBuff.io.enq.data.valid := false.B
-  txBuff.io.enq.data.bits  := 0.U
 
-  rxBuff.io.deq.data.ready := false.B
-  rxBuff.io.deq.ctrl.ready := false.B
+
+
 
 }
 
diff --git a/src/main/scala/mac/RxBuff.scala b/src/main/scala/Switch/mac/RxBuff.scala
similarity index 100%
rename from src/main/scala/mac/RxBuff.scala
rename to src/main/scala/Switch/mac/RxBuff.scala
diff --git a/src/main/scala/mac/TxBuff.scala b/src/main/scala/Switch/mac/TxBuff.scala
similarity index 100%
rename from src/main/scala/mac/TxBuff.scala
rename to src/main/scala/Switch/mac/TxBuff.scala
diff --git a/src/main/scala/mac/Parameters.scala b/src/main/scala/mac/Parameters.scala
deleted file mode 100644
index c21ab29..0000000
--- a/src/main/scala/mac/Parameters.scala
+++ /dev/null
@@ -1,32 +0,0 @@
-package MAC
-
-import chisel3._
-import chisel3.stage._
-import freechips.rocketchip.diplomacy._
-
-import org.chipsalliance.cde.config._
-
-// abstract class MacModule(implicit val p: Parameters) extends Module with HasMacParameters { def io: Record }
-// abstract class MacBundle(implicit val p: Parameters) extends Bundle with HasMacParameters
-
-
-case object MacParamsKey extends Field[MacSetting]
-
-
-case class MacSetting(
-  // isTileLink: Boolean = true
-){
-
-}
-
-trait HasMacParameters {
-  implicit val p: Parameters
-
-  val macSetting = p(MacParamsKey)
-
-  // def isTileLink = macSetting.isTileLink
-}
-
-class MacCfg extends Config((_, _, _) => {
-  case MacParamsKey => MacSetting()
-})
diff --git a/src/main/scala/mac/WithMac.scala b/src/main/scala/mac/WithMac.scala
deleted file mode 100644
index c10702a..0000000
--- a/src/main/scala/mac/WithMac.scala
+++ /dev/null
@@ -1,43 +0,0 @@
-package MAC
-
-import chisel3._
-
-import freechips.rocketchip.subsystem.BaseSubsystem
-import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.tilelink._
-import org.chipsalliance.cde.config._
-
-
-trait WithManyMacMix { this: BaseSubsystem =>
-
-    val mac0 = LazyModule(new Mac)
-
-    // sbus.coupleFrom("mac_mst") { _ := TLBuffer() := mac0.tlClientNode }
-    // pbus.coupleTo("mac_cfg")   { mac0.tlMasterNode := TLFragmenter(pbus) := _ }
-    pbus.coupleTo("mac_cfg")   { mac0.ethReg.configNode   := TLFragmenter(pbus) := _ }
-
-    ibus.fromSync := mac0.ethReg.int_node
-
-}
-
-
-trait WithManyMacMixModuleImp extends LazyModuleImp {
-  val outer: WithManyMacMix
-
-  val macIO = IO(new MacIO)
-
-  macIO <> outer.mac0.module.io
-
-  println("Warning, did you delete the rocket-chip.jar on top to reflash?")
-  println("Warning, did you delete the rocket-chip.jar on top to reflash?")
-  println("Warning, did you delete the rocket-chip.jar on top to reflash?")
-  println("Warning, did you delete the rocket-chip.jar on top to reflash?")
-  println("Warning, did you delete the rocket-chip.jar on top to reflash?")
-
-}
-
-class MacConfig() extends Config((site, here, up) => {
-  case MacParamsKey => MacSetting()
-})
-
-