拓扑修改，编译通过
This commit is contained in:
RuigeLee
@@ -9,8 +9,7 @@ import org.chipsalliance.cde.config._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.interrupts._
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class MacRegIO extends Bundle{
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class Mac_Config_Bundle extends Bundle{
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val WCtrlDataStart = Input(Bool())
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val RStatStart = Input(Bool())
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val UpdateMIIRX_DATAReg = Input(Bool())
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@@ -68,10 +67,14 @@ class MacRegIO extends Bundle{
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val r_CtrlData = Output(UInt(16.W))
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val r_MAC = Output(UInt(48.W))
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val r_TxBDNum = Output(UInt(8.W))
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// val int_o = Output(Bool())
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val r_TxPauseTV = Output(UInt(16.W))
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val r_TxPauseRq = Output(Bool())
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}
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class MacRegIO extends Mac_Config_Bundle{
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val asyncReset = Input(AsyncReset())
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}
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34
src/main/scala/Switch/Parameters.scala
Normal file
34
src/main/scala/Switch/Parameters.scala
Normal file
@@ -0,0 +1,34 @@
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package Switch
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import chisel3._
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import chisel3.stage._
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import freechips.rocketchip.diplomacy._
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import org.chipsalliance.cde.config._
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abstract class SwitchModule(implicit val p: Parameters) extends Module with HasSwitchParameters { def io: Record }
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abstract class SwitchBundle(implicit val p: Parameters) extends Bundle with HasSwitchParameters
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case object SwitchParamsKey extends Field[SwitchSetting]
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case class SwitchSetting(
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// isTileLink: Boolean = true
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chn: Int = 1
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){
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}
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trait HasSwitchParameters {
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implicit val p: Parameters
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val switchSetting = p(SwitchParamsKey)
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def chn = switchSetting.chn
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}
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class SwitchCfg extends Config((_, _, _) => {
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case SwitchParamsKey => SwitchSetting()
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})
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81
src/main/scala/Switch/Switch.scala
Normal file
81
src/main/scala/Switch/Switch.scala
Normal file
@@ -0,0 +1,81 @@
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package Switch
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import chisel3._
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import chisel3.util._
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import MAC._
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import org.chipsalliance.cde.config._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.interrupts._
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import chisel3.experimental.dataview._
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class SwitchIO(implicit p: Parameters) extends SwitchBundle{
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val mii = Vec( chn, new MII )
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val isLoopBack = Output(Vec( chn, Bool()))
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val asyncReset = Input(AsyncReset())
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}
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class Switch(implicit p: Parameters) extends LazyModule with HasSwitchParameters{
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val ethReg = LazyModule(new MacReg)
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lazy val module = new SwitchImp(this)
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}
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class SwitchImp(outer: Switch)(implicit p: Parameters) extends LazyModuleImp(outer) with HasSwitchParameters{
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val io = IO(new SwitchIO)
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val mac = ( 0 until chn ).map{ i =>
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Module(new Mac)
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}
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( 0 until chn ).map{ i =>
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mac(i).io.mii <> io.mii(i)
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mac(i).io.asyncReset := io.asyncReset
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io.isLoopBack(i) := mac(i).io.isLoopBack
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}
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outer.ethReg.module.io.asyncReset := io.asyncReset
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outer.ethReg.module.io.viewAsSupertype(new Mac_Config_Bundle) <> mac(0).io.cfg
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val rxBuff = Module(new RxBuff)
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rxBuff.io.enq <> mac(0).io.rxEnq
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rxBuff.io.deq.data.ready := false.B
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rxBuff.io.deq.ctrl.ready := false.B
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val txBuff = Module(new TxBuff)
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txBuff.io.deq <> mac(0).io.txDeq
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txBuff.io.enq.ctrl.valid := false.B
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txBuff.io.enq.data.valid := false.B
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txBuff.io.enq.data.bits := 0.U
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}
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43
src/main/scala/Switch/WithSwitch.scala
Normal file
43
src/main/scala/Switch/WithSwitch.scala
Normal file
@@ -0,0 +1,43 @@
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package Switch
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import chisel3._
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import freechips.rocketchip.subsystem.BaseSubsystem
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import org.chipsalliance.cde.config._
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trait WithSwitchMix { this: BaseSubsystem =>
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val switch = LazyModule(new Switch)
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// sbus.coupleFrom("switch_mst") { _ := TLBuffer() := switch0.tlClientNode }
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// pbus.coupleTo("switch_cfg") { switch0.tlMasterNode := TLFragmenter(pbus) := _ }
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pbus.coupleTo("switch_cfg") { switch.ethReg.configNode := TLFragmenter(pbus) := _ }
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ibus.fromSync := switch.ethReg.int_node
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}
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trait WithSwitchMixModuleImp extends LazyModuleImp {
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val outer: WithSwitchMix
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val switchIO = IO(new SwitchIO)
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switchIO <> outer.switch.module.io
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println("Warning, did you delete the rocket-chip.jar on top to reflash?")
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println("Warning, did you delete the rocket-chip.jar on top to reflash?")
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println("Warning, did you delete the rocket-chip.jar on top to reflash?")
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println("Warning, did you delete the rocket-chip.jar on top to reflash?")
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println("Warning, did you delete the rocket-chip.jar on top to reflash?")
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}
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class SwitchConfig() extends Config((site, here, up) => {
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case SwitchParamsKey => SwitchSetting()
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})
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@@ -3,28 +3,11 @@ package MAC
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import chisel3._
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import chisel3.util._
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import org.chipsalliance.cde.config._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.interrupts._
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class Mac(implicit p: Parameters) extends LazyModule with HasMacParameters{
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val ethReg = LazyModule(new MacReg)
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lazy val module = new MacImp(this)
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import Switch._
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}
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class MacIO extends Bundle with MDIO{
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class MII extends Bundle with MDIO{
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// Tx
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val mtx_clk_pad_i = Input(Bool())
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val mtxd_pad_o = Output(UInt(4.W))
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@@ -39,7 +22,16 @@ class MacIO extends Bundle with MDIO{
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// Common Tx and Rx
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val mcoll_pad_i = Input(Bool())
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val mcrs_pad_i = Input(Bool())
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val mcrs_pad_i = Input(Bool())
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}
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class MacIO extends Bundle{
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val mii = new MII
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val cfg = Flipped(new Mac_Config_Bundle)
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val rxEnq = new Receive_Enq_Bundle
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val txDeq = Flipped(new Transmit_Deq_Bundle)
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// val int_o = Output(Bool())
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@@ -47,7 +39,8 @@ class MacIO extends Bundle with MDIO{
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val asyncReset = Input(AsyncReset())
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}
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class MacImp(outer: Mac)(implicit p: Parameters) extends LazyModuleImp(outer) with HasMacParameters{
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class Mac extends Module{
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val io = IO(new MacIO)
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@@ -124,7 +117,7 @@ val miim = Module(new MIIM)
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miim.io.RStat := r_RStat
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miim.io.ScanStat := r_ScanStat
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miim.io.mdi := io.mdi
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miim.io.mdi := io.mii.mdi
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Busy_stat := miim.io.Busy
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LinkFail := miim.io.LinkFail
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@@ -134,9 +127,9 @@ val miim = Module(new MIIM)
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RStatStart := miim.io.RStatStart
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UpdateMIIRX_DATAReg := miim.io.UpdateMIIRX_DATAReg
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io.mdc := miim.io.mdc
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io.mdo := miim.io.mdo
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io.mdoEn := miim.io.mdoEn
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io.mii.mdc := miim.io.mdc
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io.mii.mdo := miim.io.mdo
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io.mii.mdoEn := miim.io.mdoEn
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@@ -288,69 +281,65 @@ dontTouch(CarrierSenseLost )
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outer.ethReg.module.io.asyncReset := io.asyncReset
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outer.ethReg.module.io.WCtrlDataStart := WCtrlDataStart
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outer.ethReg.module.io.RStatStart := RStatStart
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outer.ethReg.module.io.UpdateMIIRX_DATAReg := UpdateMIIRX_DATAReg
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outer.ethReg.module.io.Prsd := Prsd
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outer.ethReg.module.io.NValid_stat := NValid_stat
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outer.ethReg.module.io.Busy_stat := Busy_stat
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outer.ethReg.module.io.LinkFail := LinkFail
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outer.ethReg.module.io.TxB_IRQ := TxB_IRQ
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outer.ethReg.module.io.TxE_IRQ := TxE_IRQ
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outer.ethReg.module.io.RxB_IRQ := RxB_IRQ
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outer.ethReg.module.io.RxE_IRQ := RxE_IRQ
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outer.ethReg.module.io.Busy_IRQ := Busy_IRQ
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outer.ethReg.module.io.RstTxPauseRq := RstTxPauseRq
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outer.ethReg.module.io.TxCtrlEndFrm := TxCtrlEndFrm
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outer.ethReg.module.io.StartTxDone := StartTxDone
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outer.ethReg.module.io.TxClk := io.mtx_clk_pad_i
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outer.ethReg.module.io.RxClk := io.mrx_clk_pad_i
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outer.ethReg.module.io.SetPauseTimer := SetPauseTimer
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io.cfg.WCtrlDataStart := WCtrlDataStart
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io.cfg.RStatStart := RStatStart
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io.cfg.UpdateMIIRX_DATAReg := UpdateMIIRX_DATAReg
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io.cfg.Prsd := Prsd
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io.cfg.NValid_stat := NValid_stat
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io.cfg.Busy_stat := Busy_stat
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io.cfg.LinkFail := LinkFail
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io.cfg.TxB_IRQ := TxB_IRQ
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io.cfg.TxE_IRQ := TxE_IRQ
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io.cfg.RxB_IRQ := RxB_IRQ
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io.cfg.RxE_IRQ := RxE_IRQ
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io.cfg.Busy_IRQ := Busy_IRQ
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io.cfg.RstTxPauseRq := RstTxPauseRq
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io.cfg.TxCtrlEndFrm := TxCtrlEndFrm
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io.cfg.StartTxDone := StartTxDone
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io.cfg.TxClk := io.mii.mtx_clk_pad_i
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io.cfg.RxClk := io.mii.mrx_clk_pad_i
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io.cfg.SetPauseTimer := SetPauseTimer
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r_RecSmall := outer.ethReg.module.io.r_RecSmall
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r_Pad := outer.ethReg.module.io.r_Pad
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r_HugEn := outer.ethReg.module.io.r_HugEn
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r_CrcEn := outer.ethReg.module.io.r_CrcEn
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r_DlyCrcEn := outer.ethReg.module.io.r_DlyCrcEn
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r_FullD := outer.ethReg.module.io.r_FullD
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r_ExDfrEn := outer.ethReg.module.io.r_ExDfrEn
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r_NoBckof := outer.ethReg.module.io.r_NoBckof
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r_LoopBck := outer.ethReg.module.io.r_LoopBck
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r_IFG := outer.ethReg.module.io.r_IFG
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r_Pro := outer.ethReg.module.io.r_Pro
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r_Bro := outer.ethReg.module.io.r_Bro
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r_NoPre := outer.ethReg.module.io.r_NoPre
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r_TxEn := outer.ethReg.module.io.r_TxEn
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r_RxEn := outer.ethReg.module.io.r_RxEn
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r_HASH0 := outer.ethReg.module.io.r_HASH0
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r_HASH1 := outer.ethReg.module.io.r_HASH1
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r_IPGT := outer.ethReg.module.io.r_IPGT
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r_IPGR1 := outer.ethReg.module.io.r_IPGR1
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r_IPGR2 := outer.ethReg.module.io.r_IPGR2
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r_MinFL := outer.ethReg.module.io.r_MinFL
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r_MaxFL := outer.ethReg.module.io.r_MaxFL
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r_MaxRet := outer.ethReg.module.io.r_MaxRet
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r_CollValid := outer.ethReg.module.io.r_CollValid
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r_TxFlow := outer.ethReg.module.io.r_TxFlow
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r_RxFlow := outer.ethReg.module.io.r_RxFlow
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r_PassAll := outer.ethReg.module.io.r_PassAll
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r_MiiNoPre := outer.ethReg.module.io.r_MiiNoPre
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r_ClkDiv := outer.ethReg.module.io.r_ClkDiv
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r_WCtrlData := outer.ethReg.module.io.r_WCtrlData
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r_RStat := outer.ethReg.module.io.r_RStat
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r_ScanStat := outer.ethReg.module.io.r_ScanStat
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r_RGAD := outer.ethReg.module.io.r_RGAD
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r_FIAD := outer.ethReg.module.io.r_FIAD
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r_CtrlData := outer.ethReg.module.io.r_CtrlData
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r_MAC := outer.ethReg.module.io.r_MAC
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r_TxBDNum := outer.ethReg.module.io.r_TxBDNum
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// io.int_o := outer.ethReg.module.io.int_o
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// int(0) := outer.ethReg.module.io.int_o
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r_TxPauseTV := outer.ethReg.module.io.r_TxPauseTV
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r_TxPauseRq := outer.ethReg.module.io.r_TxPauseRq
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r_RecSmall := io.cfg.r_RecSmall
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r_Pad := io.cfg.r_Pad
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r_HugEn := io.cfg.r_HugEn
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r_CrcEn := io.cfg.r_CrcEn
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r_DlyCrcEn := io.cfg.r_DlyCrcEn
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r_FullD := io.cfg.r_FullD
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r_ExDfrEn := io.cfg.r_ExDfrEn
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r_NoBckof := io.cfg.r_NoBckof
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r_LoopBck := io.cfg.r_LoopBck
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r_IFG := io.cfg.r_IFG
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r_Pro := io.cfg.r_Pro
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r_Bro := io.cfg.r_Bro
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r_NoPre := io.cfg.r_NoPre
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r_TxEn := io.cfg.r_TxEn
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r_RxEn := io.cfg.r_RxEn
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r_HASH0 := io.cfg.r_HASH0
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r_HASH1 := io.cfg.r_HASH1
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r_IPGT := io.cfg.r_IPGT
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r_IPGR1 := io.cfg.r_IPGR1
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r_IPGR2 := io.cfg.r_IPGR2
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r_MinFL := io.cfg.r_MinFL
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r_MaxFL := io.cfg.r_MaxFL
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r_MaxRet := io.cfg.r_MaxRet
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r_CollValid := io.cfg.r_CollValid
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r_TxFlow := io.cfg.r_TxFlow
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r_RxFlow := io.cfg.r_RxFlow
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r_PassAll := io.cfg.r_PassAll
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r_MiiNoPre := io.cfg.r_MiiNoPre
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r_ClkDiv := io.cfg.r_ClkDiv
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r_WCtrlData := io.cfg.r_WCtrlData
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r_RStat := io.cfg.r_RStat
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r_ScanStat := io.cfg.r_ScanStat
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r_RGAD := io.cfg.r_RGAD
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r_FIAD := io.cfg.r_FIAD
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r_CtrlData := io.cfg.r_CtrlData
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r_MAC := io.cfg.r_MAC
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r_TxBDNum := io.cfg.r_TxBDNum
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r_TxPauseTV := io.cfg.r_TxPauseTV
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r_TxPauseRq := io.cfg.r_TxPauseRq
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@@ -405,8 +394,8 @@ dontTouch(StateData )
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// Connecting MACControl
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val maccontrol = Module(new MacControl)
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maccontrol.io.MTxClk := io.mtx_clk_pad_i
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maccontrol.io.MRxClk := io.mrx_clk_pad_i
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maccontrol.io.MTxClk := io.mii.mtx_clk_pad_i
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maccontrol.io.MRxClk := io.mii.mrx_clk_pad_i
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maccontrol.io.asyncReset := io.asyncReset
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maccontrol.io.TPauseRq := TPauseRq
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@@ -466,16 +455,16 @@ dontTouch(RxEnSync )
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io.isLoopBack := r_LoopBck
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// Muxed MII receive data valid
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MRxDV_Lb := Mux(r_LoopBck, io.mtxen_pad_o, io.mrxdv_pad_i & RxEnSync)
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MRxDV_Lb := Mux(r_LoopBck, io.mii.mtxen_pad_o, io.mii.mrxdv_pad_i & RxEnSync)
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// Muxed MII Receive Error
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MRxErr_Lb := Mux(r_LoopBck, io.mtxerr_pad_o, io.mrxerr_pad_i & RxEnSync)
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MRxErr_Lb := Mux(r_LoopBck, io.mii.mtxerr_pad_o, io.mii.mrxerr_pad_i & RxEnSync)
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// Muxed MII Receive Data
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MRxD_Lb := Mux(r_LoopBck, io.mtxd_pad_o, io.mrxd_pad_i)
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MRxD_Lb := Mux(r_LoopBck, io.mii.mtxd_pad_o, io.mii.mrxd_pad_i)
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val txethmac = withClockAndReset(io.mtx_clk_pad_i.asClock, io.asyncReset)( Module(new MacTx))
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val txethmac = withClockAndReset(io.mii.mtx_clk_pad_i.asClock, io.asyncReset)( Module(new MacTx))
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txethmac.io.TxStartFrm := TxStartFrmOut
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txethmac.io.TxEndFrm := TxEndFrmOut
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@@ -497,9 +486,9 @@ txethmac.io.MaxRet := r_MaxRet
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txethmac.io.NoBckof := r_NoBckof
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txethmac.io.ExDfrEn := r_ExDfrEn
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||||
io.mtxd_pad_o := txethmac.io.MTxD
|
||||
io.mtxen_pad_o := txethmac.io.MTxEn
|
||||
io.mtxerr_pad_o := txethmac.io.MTxErr
|
||||
io.mii.mtxd_pad_o := txethmac.io.MTxD
|
||||
io.mii.mtxen_pad_o := txethmac.io.MTxEn
|
||||
io.mii.mtxerr_pad_o := txethmac.io.MTxErr
|
||||
TxDoneIn := txethmac.io.TxDone
|
||||
TxRetry := txethmac.io.TxRetry
|
||||
TxAbortIn := txethmac.io.TxAbort
|
||||
@@ -542,7 +531,7 @@ dontTouch(RxStateSFD )
|
||||
dontTouch(RxStateData )
|
||||
dontTouch(AddressMiss )
|
||||
|
||||
val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Module(new MacRx))
|
||||
val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( Module(new MacRx))
|
||||
|
||||
rxethmac.io.MRxDV := MRxDV_Lb
|
||||
rxethmac.io.MRxD := MRxD_Lb
|
||||
@@ -576,13 +565,13 @@ val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Modul
|
||||
AddressMiss := rxethmac.io.AddressMiss
|
||||
|
||||
|
||||
withClockAndReset( io.mtx_clk_pad_i.asClock, reset.asAsyncReset ) {
|
||||
withClockAndReset( io.mii.mtx_clk_pad_i.asClock, reset.asAsyncReset ) {
|
||||
// MII Carrier Sense Synchronization
|
||||
CarrierSense_Tx2 := ShiftRegister(io.mcrs_pad_i, 2, false.B, true.B)
|
||||
CarrierSense_Tx2 := ShiftRegister(io.mii.mcrs_pad_i, 2, false.B, true.B)
|
||||
|
||||
TxCarrierSense := ~r_FullD & CarrierSense_Tx2
|
||||
|
||||
val Collision_Tx1 = RegNext(io.mcoll_pad_i, false.B)
|
||||
val Collision_Tx1 = RegNext(io.mii.mcoll_pad_i, false.B)
|
||||
val Collision_Tx2 = RegInit(false.B)
|
||||
|
||||
when(ResetCollision){
|
||||
@@ -600,11 +589,11 @@ val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Modul
|
||||
|
||||
|
||||
|
||||
withClockAndReset( io.mrx_clk_pad_i.asClock, reset.asAsyncReset ) {
|
||||
withClockAndReset( io.mii.mrx_clk_pad_i.asClock, reset.asAsyncReset ) {
|
||||
val WillTransmit_q = ShiftRegister(WillTransmit, 2, false.B, true.B)
|
||||
|
||||
Transmitting := ~r_FullD & WillTransmit_q
|
||||
RxEnSync := RegEnable( ShiftRegister(r_RxEn, 2), false.B, ~io.mrxdv_pad_i)
|
||||
RxEnSync := RegEnable( ShiftRegister(r_RxEn, 2), false.B, ~io.mii.mrxdv_pad_i)
|
||||
}
|
||||
|
||||
|
||||
@@ -618,7 +607,7 @@ val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Modul
|
||||
}
|
||||
|
||||
|
||||
withClockAndReset( io.mtx_clk_pad_i.asClock, reset.asAsyncReset ) {
|
||||
withClockAndReset( io.mii.mtx_clk_pad_i.asClock, reset.asAsyncReset ) {
|
||||
val TxPauseRq_sync = ShiftRegisters((r_TxPauseRq & r_TxFlow), 3, false.B, true.B )
|
||||
|
||||
TPauseRq := RegNext( TxPauseRq_sync(1) & (~TxPauseRq_sync(2)), false.B )
|
||||
@@ -632,7 +621,7 @@ val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Modul
|
||||
val RxAbort_latch_wire = Wire(Bool())
|
||||
val RxAbort_wb = ShiftRegister( RxAbort_latch_wire, 2, false.B, true.B )
|
||||
|
||||
withClockAndReset( io.mrx_clk_pad_i.asClock, reset.asAsyncReset ) {
|
||||
withClockAndReset( io.mii.mrx_clk_pad_i.asClock, reset.asAsyncReset ) {
|
||||
val RxAbort_latch = RegInit(false.B); RxAbort_latch_wire := RxAbort_latch
|
||||
val RxAbortRst = ShiftRegister( RxAbort_wb, 2, false.B, true.B )
|
||||
|
||||
@@ -673,7 +662,7 @@ val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Modul
|
||||
val macstatus = Module(new MacStatus)
|
||||
|
||||
macstatus.io.asyncReset := io.asyncReset
|
||||
macstatus.io.MRxClk := io.mrx_clk_pad_i
|
||||
macstatus.io.MRxClk := io.mii.mrx_clk_pad_i
|
||||
macstatus.io.RxCrcError := RxCrcError
|
||||
macstatus.io.MRxErr := MRxErr_Lb
|
||||
macstatus.io.MRxDV := MRxDV_Lb
|
||||
@@ -687,7 +676,7 @@ val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Modul
|
||||
macstatus.io.RxByteCntGreat2 := RxByteCntGreat2
|
||||
macstatus.io.RxByteCntMaxFrame := RxByteCntMaxFrame
|
||||
macstatus.io.MRxD := MRxD_Lb
|
||||
macstatus.io.Collision := io.mcoll_pad_i
|
||||
macstatus.io.Collision := io.mii.mcoll_pad_i
|
||||
macstatus.io.CollValid := r_CollValid
|
||||
macstatus.io.r_RecSmall := r_RecSmall
|
||||
macstatus.io.r_MinFL := r_MinFL
|
||||
@@ -696,7 +685,7 @@ val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Modul
|
||||
macstatus.io.StartTxDone := StartTxDone
|
||||
macstatus.io.StartTxAbort := StartTxAbort
|
||||
macstatus.io.RetryCnt := RetryCnt
|
||||
macstatus.io.MTxClk := io.mtx_clk_pad_i
|
||||
macstatus.io.MTxClk := io.mii.mtx_clk_pad_i
|
||||
macstatus.io.MaxCollisionOccured := MaxCollisionOccured
|
||||
macstatus.io.LateCollision := LateCollision
|
||||
macstatus.io.DeferIndication := DeferIndication
|
||||
@@ -745,13 +734,13 @@ val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Modul
|
||||
|
||||
|
||||
|
||||
val macTileLinkTx = withClockAndReset( io.mtx_clk_pad_i.asClock, io.asyncReset ) (Module(new MacTileLinkTx))
|
||||
val macTileLinkTx = withClockAndReset( io.mii.mtx_clk_pad_i.asClock, io.asyncReset ) (Module(new MacTileLinkTx))
|
||||
|
||||
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
|
||||
val ReadTxDataFromFifo_sync = ShiftRegister( macTileLinkTx.io.ReadTxDataFromFifo_tck, 2, false.B, true.B)
|
||||
wishbone.io.ReadTxDataFromFifo_sync := ReadTxDataFromFifo_sync
|
||||
|
||||
withClockAndReset( io.mtx_clk_pad_i.asClock, io.asyncReset ){
|
||||
withClockAndReset( io.mii.mtx_clk_pad_i.asClock, io.asyncReset ){
|
||||
macTileLinkTx.io.BlockingTxStatusWrite_sync := ShiftRegister( wishbone.io.BlockingTxStatusWrite, 2, false.B, true.B)
|
||||
macTileLinkTx.io.TxStartFrm_sync := ShiftRegister( wishbone.io.TxStartFrm_wb, 2, false.B, true.B ) // Synchronizing TxStartFrm_wb to MTxClk
|
||||
macTileLinkTx.io.ReadTxDataFromFifo_syncb := ShiftRegister( ReadTxDataFromFifo_sync, 2, false.B, true.B)
|
||||
@@ -802,7 +791,7 @@ val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Modul
|
||||
|
||||
|
||||
|
||||
val macTileLinkRx = withClockAndReset( io.mrx_clk_pad_i.asClock, io.asyncReset ) ( Module(new MacTileLinkRx) )
|
||||
val macTileLinkRx = withClockAndReset( io.mii.mrx_clk_pad_i.asClock, io.asyncReset ) ( Module(new MacTileLinkRx) )
|
||||
|
||||
|
||||
|
||||
@@ -830,7 +819,7 @@ val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Modul
|
||||
val Busy_IRQ_sync = ShiftRegister(macTileLinkRx.io.Busy_IRQ_rck, 2, false.B, true.B)
|
||||
Busy_IRQ := Busy_IRQ_sync & ~RegNext(Busy_IRQ_sync, false.B)
|
||||
|
||||
withClockAndReset( io.mrx_clk_pad_i.asClock, io.asyncReset ) {
|
||||
withClockAndReset( io.mii.mrx_clk_pad_i.asClock, io.asyncReset ) {
|
||||
val ShiftEndedSyncb = ShiftRegister( ShiftEndedSync, 2, false.B, true.B)
|
||||
RxStatusWriteLatchedSync := ShiftEndedSyncb
|
||||
macTileLinkRx.io.ShiftEndedSyncb := ShiftEndedSyncb
|
||||
@@ -854,12 +843,8 @@ val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Modul
|
||||
macTileLinkRx.io.RxStatusIn := Cat(ReceivedPauseFrm, AddressMiss, false.B, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision)
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
wishbone.io.rxEnq <> io.rxEnq
|
||||
wishbone.io.txDeq <> io.txDeq
|
||||
}
|
||||
|
||||
|
||||
@@ -56,7 +56,8 @@ abstract class MacTileLinkBase() extends Module{
|
||||
val TxDoneSync = Input(Bool()) // Transmission ended
|
||||
|
||||
|
||||
|
||||
val rxEnq = new Receive_Enq_Bundle
|
||||
val txDeq = Flipped(new Transmit_Deq_Bundle)
|
||||
|
||||
}
|
||||
|
||||
@@ -64,8 +65,8 @@ abstract class MacTileLinkBase() extends Module{
|
||||
|
||||
val io = IO(new MacTileLinkIO)
|
||||
|
||||
val txBuff = Module(new TxBuff)
|
||||
val rxBuff = Module(new RxBuff)
|
||||
|
||||
|
||||
|
||||
val ShiftEndedSyncPluse = io.ShiftEndedSync & ~RegNext(io.ShiftEndedSync, false.B)
|
||||
val RxAbortPluse = io.RxAbortSync & ~RegNext(io.RxAbortSync, false.B)
|
||||
@@ -75,12 +76,12 @@ abstract class MacTileLinkBase() extends Module{
|
||||
|
||||
|
||||
val rxBuffCtrlValid = RegInit(false.B)
|
||||
rxBuff.io.enq.ctrl.valid := rxBuffCtrlValid
|
||||
rxBuff.io.enq.ctrl.bits.LatchedRxLength := RegEnable(io.LatchedRxLength_rxclk, ShiftEndedSyncPluse | RxAbortPluse)
|
||||
rxBuff.io.enq.ctrl.bits.RxStatusInLatched := RegEnable(io.RxStatusInLatched_rxclk, ShiftEndedSyncPluse | RxAbortPluse)
|
||||
rxBuff.io.enq.ctrl.bits.isRxAbort := RegEnable(RxAbortPluse, false.B, ShiftEndedSyncPluse | RxAbortPluse)
|
||||
io.rxEnq.ctrl.valid := rxBuffCtrlValid
|
||||
io.rxEnq.ctrl.bits.LatchedRxLength := RegEnable(io.LatchedRxLength_rxclk, ShiftEndedSyncPluse | RxAbortPluse)
|
||||
io.rxEnq.ctrl.bits.RxStatusInLatched := RegEnable(io.RxStatusInLatched_rxclk, ShiftEndedSyncPluse | RxAbortPluse)
|
||||
io.rxEnq.ctrl.bits.isRxAbort := RegEnable(RxAbortPluse, false.B, ShiftEndedSyncPluse | RxAbortPluse)
|
||||
|
||||
when( rxBuff.io.enq.ctrl.fire ){
|
||||
when( io.rxEnq.ctrl.fire ){
|
||||
rxBuffCtrlValid := false.B
|
||||
} .elsewhen( ShiftEndedSyncPluse | RxAbortPluse ){
|
||||
rxBuffCtrlValid := true.B
|
||||
@@ -91,15 +92,15 @@ abstract class MacTileLinkBase() extends Module{
|
||||
// RxReady generation
|
||||
when(ShiftEndedSyncPluse | RxAbortPluse ){
|
||||
RxReady := false.B
|
||||
} .elsewhen( io.r_RxEn & (rxBuff.io.enq.data.ready) ){
|
||||
} .elsewhen( io.r_RxEn & (io.rxEnq.data.ready) ){
|
||||
RxReady := true.B
|
||||
}
|
||||
|
||||
|
||||
rxBuff.io.enq.data.bits := io.RxDataLatched2_rxclk
|
||||
rxBuff.io.enq.data.valid := WriteRxDataToFifoSyncPluse
|
||||
io.rxEnq.data.bits := io.RxDataLatched2_rxclk
|
||||
io.rxEnq.data.valid := WriteRxDataToFifoSyncPluse
|
||||
|
||||
assert( ~(rxBuff.io.enq.data.valid & ~rxBuff.io.enq.data.ready), "Assert Failed, rx overrun!" )
|
||||
assert( ~(io.rxEnq.data.valid & ~io.rxEnq.data.ready), "Assert Failed, rx overrun!" )
|
||||
|
||||
|
||||
|
||||
@@ -133,10 +134,10 @@ abstract class MacTileLinkBase() extends Module{
|
||||
val ReadTxDataFromFifoSyncPluse = io.ReadTxDataFromFifo_sync & ~RegNext(io.ReadTxDataFromFifo_sync, false.B)
|
||||
|
||||
|
||||
io.PerPacketPad := RegEnable(txBuff.io.deq.req.bits.PerPacketPad, false.B, txBuff.io.deq.req.fire)
|
||||
io.PerPacketCrcEn := RegEnable(txBuff.io.deq.req.bits.PerPacketCrcEn, false.B, txBuff.io.deq.req.fire)
|
||||
io.PerPacketPad := RegEnable(io.txDeq.req.bits.PerPacketPad, false.B, io.txDeq.req.fire)
|
||||
io.PerPacketCrcEn := RegEnable(io.txDeq.req.bits.PerPacketCrcEn, false.B, io.txDeq.req.fire)
|
||||
|
||||
when( txBuff.io.deq.req.fire ){
|
||||
when( io.txDeq.req.fire ){
|
||||
TxStartFrm_wb := true.B
|
||||
} .elsewhen(io.TxStartFrm_syncb){
|
||||
TxStartFrm_wb := false.B
|
||||
@@ -149,11 +150,11 @@ abstract class MacTileLinkBase() extends Module{
|
||||
TxEndFrm_wb := false.B
|
||||
}
|
||||
|
||||
when( txBuff.io.deq.req.fire ){
|
||||
when( io.txDeq.req.fire ){
|
||||
|
||||
TxLength := txBuff.io.deq.req.bits.txLength
|
||||
LatchedTxLength := txBuff.io.deq.req.bits.txLength
|
||||
} .elsewhen( txBuff.io.deq.data.fire ){
|
||||
TxLength := io.txDeq.req.bits.txLength
|
||||
LatchedTxLength := io.txDeq.req.bits.txLength
|
||||
} .elsewhen( io.txDeq.data.fire ){
|
||||
when( TxLength < 4.U ){
|
||||
TxLength := 0.U
|
||||
} .otherwise{
|
||||
@@ -165,10 +166,10 @@ abstract class MacTileLinkBase() extends Module{
|
||||
val txRespValid = RegInit(false.B)
|
||||
val txRespBits = Reg(new Transmit_Deq_Resp_Bundle)
|
||||
|
||||
txBuff.io.deq.resp.valid := txRespValid
|
||||
txBuff.io.deq.resp.bits := txRespBits
|
||||
io.txDeq.resp.valid := txRespValid
|
||||
io.txDeq.resp.bits := txRespBits
|
||||
|
||||
when( txBuff.io.deq.resp.fire ){
|
||||
when( io.txDeq.resp.fire ){
|
||||
txRespValid := false.B
|
||||
} .elsewhen( txRetryPulse | txDonePulse | txAbortPulse ){
|
||||
txRespValid := true.B
|
||||
@@ -185,9 +186,9 @@ abstract class MacTileLinkBase() extends Module{
|
||||
|
||||
|
||||
|
||||
val isTxBusy = RegInit(false.B); txBuff.io.deq.req.ready := ~isTxBusy & io.r_TxEn
|
||||
val isTxBusy = RegInit(false.B); io.txDeq.req.ready := ~isTxBusy & io.r_TxEn
|
||||
|
||||
when(txBuff.io.deq.req.fire){
|
||||
when( io.txDeq.req.fire){
|
||||
isTxBusy := true.B
|
||||
} .elsewhen(txRetryPulse | txDonePulse | txAbortPulse){
|
||||
isTxBusy := false.B
|
||||
@@ -199,10 +200,10 @@ abstract class MacTileLinkBase() extends Module{
|
||||
|
||||
|
||||
|
||||
txBuff.io.deq.data.ready := ReadTxDataFromFifoSyncPluse
|
||||
assert( ~(txBuff.io.deq.data.ready & ~txBuff.io.deq.data.valid), "Assert Failed, Tx should never under run!" )
|
||||
io.txDeq.data.ready := ReadTxDataFromFifoSyncPluse
|
||||
assert( ~(io.txDeq.data.ready & ~io.txDeq.data.valid), "Assert Failed, Tx should never under run!" )
|
||||
|
||||
io.TxData_wb := txBuff.io.deq.data.bits
|
||||
io.TxData_wb := io.txDeq.data.bits
|
||||
|
||||
|
||||
|
||||
@@ -252,12 +253,9 @@ abstract class MacTileLinkBase() extends Module{
|
||||
|
||||
|
||||
class MacTileLink() extends MacTileLinkBase(){
|
||||
txBuff.io.enq.ctrl.valid := false.B
|
||||
txBuff.io.enq.data.valid := false.B
|
||||
txBuff.io.enq.data.bits := 0.U
|
||||
|
||||
rxBuff.io.deq.data.ready := false.B
|
||||
rxBuff.io.deq.ctrl.ready := false.B
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
@@ -1,32 +0,0 @@
|
||||
package MAC
|
||||
|
||||
import chisel3._
|
||||
import chisel3.stage._
|
||||
import freechips.rocketchip.diplomacy._
|
||||
|
||||
import org.chipsalliance.cde.config._
|
||||
|
||||
// abstract class MacModule(implicit val p: Parameters) extends Module with HasMacParameters { def io: Record }
|
||||
// abstract class MacBundle(implicit val p: Parameters) extends Bundle with HasMacParameters
|
||||
|
||||
|
||||
case object MacParamsKey extends Field[MacSetting]
|
||||
|
||||
|
||||
case class MacSetting(
|
||||
// isTileLink: Boolean = true
|
||||
){
|
||||
|
||||
}
|
||||
|
||||
trait HasMacParameters {
|
||||
implicit val p: Parameters
|
||||
|
||||
val macSetting = p(MacParamsKey)
|
||||
|
||||
// def isTileLink = macSetting.isTileLink
|
||||
}
|
||||
|
||||
class MacCfg extends Config((_, _, _) => {
|
||||
case MacParamsKey => MacSetting()
|
||||
})
|
||||
@@ -1,43 +0,0 @@
|
||||
package MAC
|
||||
|
||||
import chisel3._
|
||||
|
||||
import freechips.rocketchip.subsystem.BaseSubsystem
|
||||
import freechips.rocketchip.diplomacy._
|
||||
import freechips.rocketchip.tilelink._
|
||||
import org.chipsalliance.cde.config._
|
||||
|
||||
|
||||
trait WithManyMacMix { this: BaseSubsystem =>
|
||||
|
||||
val mac0 = LazyModule(new Mac)
|
||||
|
||||
// sbus.coupleFrom("mac_mst") { _ := TLBuffer() := mac0.tlClientNode }
|
||||
// pbus.coupleTo("mac_cfg") { mac0.tlMasterNode := TLFragmenter(pbus) := _ }
|
||||
pbus.coupleTo("mac_cfg") { mac0.ethReg.configNode := TLFragmenter(pbus) := _ }
|
||||
|
||||
ibus.fromSync := mac0.ethReg.int_node
|
||||
|
||||
}
|
||||
|
||||
|
||||
trait WithManyMacMixModuleImp extends LazyModuleImp {
|
||||
val outer: WithManyMacMix
|
||||
|
||||
val macIO = IO(new MacIO)
|
||||
|
||||
macIO <> outer.mac0.module.io
|
||||
|
||||
println("Warning, did you delete the rocket-chip.jar on top to reflash?")
|
||||
println("Warning, did you delete the rocket-chip.jar on top to reflash?")
|
||||
println("Warning, did you delete the rocket-chip.jar on top to reflash?")
|
||||
println("Warning, did you delete the rocket-chip.jar on top to reflash?")
|
||||
println("Warning, did you delete the rocket-chip.jar on top to reflash?")
|
||||
|
||||
}
|
||||
|
||||
class MacConfig() extends Config((site, here, up) => {
|
||||
case MacParamsKey => MacSetting()
|
||||
})
|
||||
|
||||
|
||||
Reference in New Issue
Block a user