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拓扑修改，编译通过

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This commit is contained in:
RuigeLee
2023-10-19 15:24:26 +08:00
parent d77c69aa5a
commit 70922ecb44
22 changed files with 303 additions and 228 deletions
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10
Makefile
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@@ -3,8 +3,14 @@
compile:
rm -rf ./generated/
sbt "test:runMain test.testModule"
rm -rf ./rocket-chip/vsim/generated-src/
mkdir -p ./generated/
cd ./rocket-chip/ && rm -f rocketchip.jar
cd ./rocket-chip/vsim && make verilog CONFIG=freechips.rocketchip.system.UserFPGAConfig
cp ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.UserFPGAConfig.v ./generated/UserFPGAConfig.v
cp ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.UserFPGAConfig.behav_srams.v ./generated/behav_srams.v
# sbt "test:runMain test.testModule"
VSimTop: