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bacon
2025-02-09 01:17:17 +08:00
parent 55675b93c9
commit 6e72db048a
9 changed files with 441 additions and 307 deletions
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135
tb/sw/tl2cdr/tl2cdr.h
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@@ -5,50 +5,113 @@
#include <stdint.h>
#endif
#define TL2CDR_BASE 0x10000000U
#define TL2CDR_BASE 0x10000000U
// volatile uint32_t *cdr_status = (uint32_t*)( 0x000 + 0x0 ); //read
// volatile uint32_t *cdr_txLen = (uint32_t*)( 0x000 + 0x4 ); //write
// volatile uint32_t *cdr_txFifo = (uint32_t*)( 0x000 + 0x8 ); //write
// volatile uint32_t *cdr_direct = (uint32_t*)( 0x000 + 0xc ); //write
#define OLD_CODE
#ifdef OLD_CODE
#define CDR_ReadStatus 0x00U
#define CDR_WriteTxLen 0x04U
#define CDR_WriteTxFifo 0x08U
#define CDR_WriteTransDir 0x0cU
#define CDR_WriteSoftReset 0x10U
#define CDR_ReadRxLen 0x18U
#define CDR_ReadRxFifo 0x1cU
#define CDR_ReadIsLast 0x20U
#define CDR_ReadTxCrc 0x24U
#define CDR_ReadRxCrc 0x28U
#define CDR_WriteLimitTimer 0x2cU
// volatile uint32_t *cdr_softReset = (uint32_t*)( 0x000 + 0x10 ); //write
// volatile uint32_t *cdr_rxLen = (uint32_t*)( 0x000 + 0x18 ); //read
// volatile uint32_t *cdr_rxFifo = (uint32_t*)( 0x000 + 0x1c ); //read
#define CDR_INT_TXEND 14U
#define CDR_INT_RXERROR 15U
#define CDR_INT_RXSTART 16U
#define CDR_INT_RXEND 17U
#endif
#define CDR_ReadStatus 0x00
#define CDR_WriteTxLen 0x04
#define CDR_WriteTxFifo 0x08
#define CDR_WriteTransDir 0x0c
#define CDR_WriteSoftReset 0x10
#define CDR_ReadRxLen 0x18
#define CDR_ReadRxFifo 0x1c
#define CDR_ReadIsLast 0x20
#define CDR_ReadTxCrc 0x24
#define CDR_ReadRxCrc 0x28
#define CDR_WriteLimitTimer 0x2c
#define CDR_INT_TXEND 14
#define CDR_INT_RXERROR 15
#define CDR_INT_RXSTART 16
#define CDR_INT_RXEND 17
#define CDR_INT_TX0END 14U
#define CDR_INT_TX1END 15U
#define CDR_INT_RX0ERROR 16U
#define CDR_INT_RX1ERROR 17U
#define CDR_INT_RX0START 18U
#define CDR_INT_RX1START 19U
#define CDR_INT_RX0END 20U
#define CDR_INT_RX1END 21U
#define CDR_INT_TX0_FIFO_DEQ 22U
#define CDR_INT_TX1_FIFO_DEQ 23U
#define CDR_INT_RX0_FIFO_ENQ 24U
#define CDR_INT_RX1_FIFO_ENQ 25U
#define TX0_WriteSoftReset 0x00U
#define TX0_WriteTxLen 0x04U
#define TX0_WriteTxFifo 0x08U
#define TX0_ReadTxCrc 0x0CU
#define TX1_WriteSoftReset 0x10U
#define TX1_WriteTxLen 0x14U
#define TX1_WriteTxFifo 0x18U
#define TX1_ReadTxCrc 0x1CU
#define RX0_WriteSoftReset 0x20U
#define RX0_ReadRxLen 0x24U
#define RX0_ReadRxFifo 0x28U
#define RX0_ReadRxCrc 0x2CU
#define RX0_WrtieLimitTimerAim 0x30U
#define RX0_WriteLimitTxPair 0x34U
#define RX1_WriteSoftReset 0x40U
#define RX1_ReadRxLen 0x44U
#define RX1_ReadRxFifo 0x48U
#define RX1_ReadRxCrc 0x4CU
#define RX1_WrtieLimitTimerAim 0x50U
#define RX1_WriteLimitTxPair 0x54U
#define HLM_ReadStatus 0x58U
#define HLM_ReadIsLast 0x5CU
#ifndef __ASSEMBLER__
extern volatile uint32_t * const cdr_status;// = (uint32_t*)( TL2CDR_BASE + CDR_ReadStatus ); //read
extern volatile uint32_t * const cdr_txLen;// = (uint32_t*)( TL2CDR_BASE + CDR_WriteTxLen ); //write
extern volatile uint32_t * const cdr_txFifo;// = (uint32_t*)( TL2CDR_BASE + CDR_WriteTxFifo ); //write
extern volatile uint32_t * const cdr_direct;// = (uint32_t*)( TL2CDR_BASE + CDR_WriteTransDir ); //write
extern volatile uint32_t * const cdr_softReset;// = (uint32_t*)( TL2CDR_BASE + CDR_WriteSoftReset ); //write
extern volatile uint32_t * const cdr_rxLen;// = (uint32_t*)( TL2CDR_BASE + CDR_ReadRxLen ); //read
extern volatile uint32_t * const cdr_rxFifo;// = (uint32_t*)( TL2CDR_BASE + CDR_ReadRxFifo ); //read
extern volatile uint32_t * const cdr_IsLast;// = (uint32_t*)( TL2CDR_BASE + CDR_ReadIsLast ); //read
extern volatile uint32_t * const cdr_rxCrc;// = (uint32_t*)( TL2CDR_BASE + CDR_ReadRxCrc );
extern volatile uint32_t * const cdr_txCrc;// = (uint32_t*)( TL2CDR_BASE + CDR_ReadTxCrc);
// extern uint8_t gpio_read();
// extern uint32_t gpio_write( uint32_t data );
#ifdef OLD_CODE
extern volatile uint32_t * const cdr_status;
extern volatile uint32_t * const cdr_txLen;
extern volatile uint32_t * const cdr_txFifo;
extern volatile uint32_t * const cdr_direct;
extern volatile uint32_t * const cdr_softReset;
extern volatile uint32_t * const cdr_rxLen;
extern volatile uint32_t * const cdr_rxFifo;
extern volatile uint32_t * const cdr_IsLast;
extern volatile uint32_t * const cdr_rxCrc;
extern volatile uint32_t * const cdr_txCrc;
#endif
// void gpio_test();
extern volatile uint32_t * const tx0_softReset;
extern volatile uint32_t * const tx0_txLen;
extern volatile uint32_t * const tx0_txFifo;
extern volatile uint32_t * const tx0_txCrc;
extern volatile uint32_t * const tx1_softReset;
extern volatile uint32_t * const tx1_txLen;
extern volatile uint32_t * const tx1_txFifo;
extern volatile uint32_t * const tx1_txCrc;
extern volatile uint32_t * const rx0_softReset;
extern volatile uint32_t * const rx0_rxLen;
extern volatile uint32_t * const rx0_rxFifo;
extern volatile uint32_t * const rx0_rxCrc;
extern volatile uint32_t * const rx0_rxTimerAim;
extern volatile uint32_t * const rx0_rxTxPair;
extern volatile uint32_t * const rx1_softReset;
extern volatile uint32_t * const rx1_rxLen;
extern volatile uint32_t * const rx1_rxFifo;
extern volatile uint32_t * const rx1_rxCrc;
extern volatile uint32_t * const rx1_rxTimerAim;
extern volatile uint32_t * const rx1_rxTxPair;
extern volatile uint32_t * const HLM_status;
extern volatile uint32_t * const HLM_isLast;
#endif
#endif