diff --git a/Makefile b/Makefile
index 85177f1..2c6dcb2 100644
--- a/Makefile
+++ b/Makefile
@@ -21,6 +21,7 @@ compile:
 	sed -e "s/CoreID = _RAND/\/\/CoreID = _RAND/g" ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.RtppConfig.v > ./generated/Rtpp/RtppConfig.v
 #	cp ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.RtppConfig.v ./generated/Rtpp/RtppConfig.v
 	cp ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.RtppConfig.behav_srams.v ./generated/Rtpp/behav_srams.v
+	cp ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.RtppConfig/MirrorSRAMDP.v ./generated/Rtpp/MirrorSRAMDP.v
 # 	sbt "test:runMain test.testModule"
 
 back:
@@ -51,6 +52,7 @@ VSimTop:
 	--cc ./tb/verilator/SimTop.v  \
 	--cc ${PWD}/generated/Rtpp/behav_srams.v  \
 	--cc ${PWD}/generated/Rtpp/RtppConfig.v  \
+	--cc ${PWD}/generated/Rtpp/MirrorSRAMDP.v \
 	+define+RANDOMIZE_GARBAGE_ASSIGN \
 	+define+RANDOMIZE_INVALID_ASSIGN \
 	+define+RANDOMIZE_REG_INIT \
diff --git a/rocket-chip b/rocket-chip
index 917ac65..0eec8c6 160000
--- a/rocket-chip
+++ b/rocket-chip
@@ -1 +1 @@
-Subproject commit 917ac659f02a9a0c9bfe736e7fa965d7692664cb
+Subproject commit 0eec8c65489e0e6ace60126d4ba500b3a0c4417c
diff --git a/tb/sw/src/MstMain.c b/tb/sw/src/MstMain.c
index e741636..e60f97f 100644
--- a/tb/sw/src/MstMain.c
+++ b/tb/sw/src/MstMain.c
@@ -1,9 +1,7 @@
-
 #include <stdint.h>
-// #include "uart.h"
-// #include "gpio.h"
-// #include "timer.h"
 #include "tl2cdr.h"
+#include "mstMainCfg.h"
+#include "sysDef.h"
 
 volatile uint32_t *plic_priority_3   = (uint32_t*)( 0xc000000U + 0X000004 * 3);
 volatile uint32_t *plic_priority_4   = (uint32_t*)( 0xc000000U + 0X000004 * 4);
@@ -27,53 +25,19 @@ volatile uint32_t *plic_enable_0_31  = (uint32_t*)( 0xc000000U + 0X002000 );
 volatile uint32_t *plic_threshold_0  = (uint32_t*)( 0xc000000U + 0X200000 );
 volatile uint32_t *plic_claim        = (uint32_t*)( 0xc000000U + 0X200004 );
 
-
-volatile uint32_t flag_intTxEnd = 0;
-volatile uint32_t flag_intRxError = 0;
-volatile uint32_t flag_intRxStart = 0;
-volatile uint32_t flag_intRxEnd = 0;
-
-
-void plic_handle(){
-
-	
-	// 从 PLIC 中获取中断源 ID
-    uint32_t claim = *plic_claim;
-
-
-	if( claim == CDR_INT_TXEND ){
-		flag_intTxEnd = 1;
-	} else if( claim == CDR_INT_RXERROR ){
-		flag_intRxError = 1;
-	} else if( claim == CDR_INT_RXSTART ){
-		flag_intRxStart = 1;
-	} else if( claim == CDR_INT_RXEND ){
-		flag_intRxEnd = 1;
-	}
-
-    // 通知 PLIC 完成中断处理
-    *plic_claim = claim;
-	return;
-}
+uint8_t MST_TX_BUF[TX_BUF_NUM * TX_BUF_MAX_LEN] __attribute__((aligned(32)));
+uint8_t MST_RX_BUF[RX_BUF_NUM * RX_BUF_MAX_LEN] __attribute__((aligned(32)));
 
 static inline void error() {
     while(1);
 }
 
 
-// extern volatile uint32_t *cdr_status = (uint32_t*)( TL2CDR_BASE + CDR_ReadStatus ); //read
-// extern volatile uint32_t *cdr_txLen  = (uint32_t*)( TL2CDR_BASE + CDR_WriteTxLen ); //write
-// extern volatile uint32_t *cdr_txFifo = (uint32_t*)( TL2CDR_BASE + CDR_WriteTxFifo ); //write
-// extern volatile uint32_t *cdr_direct = (uint32_t*)( TL2CDR_BASE + CDR_WriteTransDir ); //write
-// extern volatile uint32_t *cdr_softReset = (uint32_t*)( TL2CDR_BASE + CDR_WriteSoftReset ); //write
-// extern volatile uint32_t *cdr_rxLen     = (uint32_t*)( TL2CDR_BASE + CDR_ReadRxLen ); //read
-// extern volatile uint32_t *cdr_rxFifo    = (uint32_t*)( TL2CDR_BASE + CDR_ReadRxFifo ); //read
-
-//extern const uint8_t mst_svr_code[];
-//uint32_t (*init_svr_code)(void); 
-
+extern const uint8_t int_svr_code[];
+uint32_t (*sys_call)(uint32_t no, ...);
 void main()
 {
+	#if 0
 	uint32_t readDat;
 	uint32_t operator;
 	uint32_t downRecvLen;
@@ -84,59 +48,91 @@ void main()
 
 	uint32_t isLast;
 
-	uint32_t led = 0;
 	uint32_t crc;
+	#endif
 
-	//init_svr_code = (uint32_t (*)(void))mst_svr_code;
 
-	*plic_enable_0_31 = 1 << CDR_INT_TXEND | 1 << CDR_INT_RXERROR | 1 << CDR_INT_RXSTART | 1 << CDR_INT_RXEND;
+	int i;
+
+
+	
+
+	/*初始化plic*/
+	*plic_enable_0_31 =   1 << CDR_INT_TX0END
+						//| 1 << CDR_INT_TX1END
+
+						//| 1 << CDR_INT_RX0ERROR
+						| 1 << CDR_INT_RX1ERROR
+
+						//| 1 << CDR_INT_RX0START
+						| 1 << CDR_INT_RX1START
+
+						//| 1 << CDR_INT_RX0END
+						| 1 << CDR_INT_RX1END
+
+						| 1 << CDR_INT_TX0_FIFO_DEQ
+						//| 1 << CDR_INT_TX1_FIFO_DEQ
+
+						//| 1 << CDR_INT_RX0_FIFO_ENQ
+						| 1 << CDR_INT_RX1_FIFO_ENQ
+						;
+
 	*plic_priority_TxEnd   = 1;
 	*plic_priority_RxError = 1;
 	*plic_priority_RxStart = 1;
 	*plic_priority_RxEnd   = 1;
 	*plic_threshold_0 = 0;
 
-	{//再写一次实现延迟，等从机的复位完成
-		*plic_enable_0_31 = 1 << CDR_INT_TXEND | 1 << CDR_INT_RXERROR | 1 << CDR_INT_RXSTART | 1 << CDR_INT_RXEND;
-		*plic_priority_TxEnd   = 1;
-		*plic_priority_RxError = 1;
-		*plic_priority_RxStart = 1;
-		*plic_priority_RxEnd   = 1;
-		*plic_threshold_0 = 0;	
-	}
+	#if 0
+	//再写一次实现延迟，等从机的复位完成
+	*plic_enable_0_31 = 1 << CDR_INT_TXEND | 1 << CDR_INT_RXERROR | 1 << CDR_INT_RXSTART | 1 << CDR_INT_RXEND;
+	*plic_priority_TxEnd   = 1;
+	*plic_priority_RxError = 1;
+	*plic_priority_RxStart = 1;
+	*plic_priority_RxEnd   = 1;
+	*plic_threshold_0 = 0;	
+	#else
+	//延迟等待从机复位，初始化
+	for (i = 0; i < 100; i++)
+		asm volatile("nop");
+	#endif
 
 	//while (init_svr_code() != 1);
 
+	sys_call = (void *)int_svr_code;
 
 
-	*cdr_softReset = 1; //复位脉冲
-	*cdr_direct = 0;
+	//复位脉冲
+	*tx0_softReset = 1;
+	*tx1_softReset = 1;
+	*rx0_softReset = 1;
+	*rx1_softReset = 1;
 
-	register uint32_t flag;
 
-									// asm volatile ( //timer 2s
-									// 	"1:\n"
-									// 	"rdcycle %0\n"
-									// 	// "srli %0, %0, 12\n"
-									// 	"srli %0, %0, 27\n"
-									// 	// "srli %0, %0, 26\n"
-									// 	"andi %0, %0, 0x1\n"
-									// 	"beqz %0, 1b\n"
-									// 	:"+r"(flag)
-									// );
+	//tx0   下行
+	//tx1	上行
+	//rx0	下行
+	//rx1	上行
+	uint32_t tx_len;
+	
+	tx_len = 32;
 
-		// if( led ){
-		// 	*WriteGpio = 0xFFFFFFFF;
-		// 	led = 0;
-		// } else{
-		// 	*WriteGpio = 0x0;
-		// 	led = 1;		
-		// }
+	for (i = 0; i < tx_len / 4 - 1; i++)
+	{
+		MST_TX_BUF[i] = i;
+	}
 
-		//发送下行包头
-		*cdr_txLen = 520; //总长520
-		*cdr_txFifo = (512 << 20) |( 0 << 16) | 0x0000; //负载长度512，操作数0， 参数全0
-		*cdr_txFifo = 0x00000000;
+	sys_call(SYS_SET_RECV_INFO, MST_RX_BUF);
+	sys_call(SYS_SEND_DATA, MST_TX_BUF, tx_len);
+
+
+	while (1);
+
+
+	#if 0
+	*cdr_txLen = 520; //总长520
+	*cdr_txFifo = (512 << 20) |( 0 << 16) | 0x0000; //负载长度512，操作数0， 参数全0
+	*cdr_txFifo = 0x00000000;
 
 		for( uint32_t i = 0; i < 512/4 - 1; i ++ ){
 			*cdr_txFifo = 0x00000000;
@@ -236,6 +232,6 @@ void main()
 		flag_intRxEnd = 0;
 
 		totNum = (upRecvLen >> 3);
-
+	#endif
 
 }
\ No newline at end of file
diff --git a/tb/sw/src/mstMainCfg.h b/tb/sw/src/mstMainCfg.h
new file mode 100644
index 0000000..1b1d7dd
--- /dev/null
+++ b/tb/sw/src/mstMainCfg.h
@@ -0,0 +1,9 @@
+#ifndef __MSTMAINCFG_H__
+#define __MSTMAINCFG_H__
+
+#define TX_BUF_NUM          2
+#define TX_BUF_MAX_LEN      1024
+#define RX_BUF_NUM          2
+#define RX_BUF_MAX_LEN      1024
+
+#endif
diff --git a/tb/sw/src/mstStartup.S b/tb/sw/src/mstStartup.S
index 0f81b4b..f699552 100644
--- a/tb/sw/src/mstStartup.S
+++ b/tb/sw/src/mstStartup.S
@@ -1,13 +1,9 @@
 #include "tl2cdr.h"
 
 .extern main
-.extern plic_handle
+
 .extern int_svr_code
 .extern plic_claim
-.extern flag_intTxEnd
-.extern flag_intRxError
-.extern flag_intRxStart
-.extern flag_intRxEnd
 
 .globl _prog_start
 .section .text.init
@@ -50,32 +46,14 @@ _prog_start:
 
 	li sp, 0x40011000
 
+	li 	a0, 0
+
 	lui t0, %hi(plic_claim)
-	lw a0, %lo(plic_claim)(t0)
-	#la a0, plic_claim
-	
-	#lui t0, %hi(flag_intTxEnd)
-	#lw a1, %lo(flag_intTxEnd)(t0)
+	lw 	a1, %lo(plic_claim)(t0)
 
-	la a1, flag_intTxEnd
-	
-	#lui t0, %hi(flag_intRxError)
-	#lw a2, %lo(flag_intRxError)(t0)
-	la a2, flag_intRxError
-
-	#lui t0, %hi(flag_intRxStart)
-	#lw a3, %lo(flag_intRxStart)(t0)
-	la a3, flag_intRxStart
-
-	#lui t0, %hi(flag_intRxEnd)
-	#lw a4, %lo(flag_intRxEnd)(t0)
-	la a4, flag_intRxEnd
-	
 	call int_svr_code
 	mv t0, a0					#这里选择不同的trap_entry服务函数,这个是RV32I的代码
-
-	#la t0, trap_entry			#这个是最初版的trap_entry，仅做了RV32E的改造
-	#la t0, opt_trap_entry		#这个是做了汇编优化的，也做了RV32E的改造
+	
 	csrw mtvec, t0
 	li t0, 1 << 11
 	csrw mie, t0
@@ -89,6 +67,8 @@ _prog_start:
 	ecall
 
 
+#if 0
+
 .balign 32
 .section .trap_entry, "ax", %progbits
 trap_entry:
@@ -314,5 +294,5 @@ opt_trap_entry:
 
 	mret
 
-
+#endif
 
diff --git a/tb/sw/src/mstSvr.S b/tb/sw/src/mstSvr.S
index d033f60..9f14f3e 100644
--- a/tb/sw/src/mstSvr.S
+++ b/tb/sw/src/mstSvr.S
@@ -1,97 +1,231 @@
 #include "tl2cdr.h"
+#include "sysDef.h"
+
+#if 0
+/*
+其他代码全部使用RV32E编译，仅此代码采用 RV32I 编译，故而可以使用x0, x16~x31寄存器
+为了方便，不再使用ABI中的别名，直接使用x0, x16~x31；x1~x15使用ABI中定义的别名
+
+x16~x23, 作为临时寄存器使用
+
+
+x24, TL2CDR_BASE
+
+x25, 接收数据的存储地址，第一个4字节接收数据的长度，往后都是数据
+
+x26, 当前需要发送的数据的地址，第一个4个字节是长度(写入tx0_txLen)、第二开始是数据
+x27, 需要发送的数据长度
+
+x28, plic_claim的地址，用于读取当前正在服务的中断号，清除中断号
+x29, REG_ISR_ADDR 中断服务子程序入口
+
+x30, 最小的服务中断号
+x31, 最大的服务中断号
+*/
+
+#endif
+
+#define REG_TL2CDR_BASE 	x24 
+#define REG_rx_data			x25
+#define REG_tx_data			x26
+#define REG_tx_data_len 	x27
+#define REG_plic_claim		x28
+#define REG_ISR_ADDR		x29
+#define REG_min_isr_num 	x30
+#define REG_max_isr_num		x31
+
 
 .globl _prog_start
 .globl _rv32i_plic_handle
 
 .section .text.init, "ax", %progbits
 
-#if 0
-#其他代码全部使用RV32E编译，仅此代码采用 RV32I 编译，故而可以使用x0, x16~x31寄存器
-#为了方便，不再使用ABI中的别名，直接使用x0, x16~x31；x1~x15使用ABI中定义的别名
-#endif
-
 _prog_start:
-	li		x16, 0
+	//a0 call_function no
+	li		x16, SYS_INIT
+	beqz 	 a0, init_system_func  //初始化系统，输入必要的地址信息，返回 中断程序 的地址
 	
-	mv 		x17, a0 # plic_claim
-	mv 		x18, a1 # flag_intTxEnd
-	mv 		x19, a2 # flag_intRxError
-	mv 		x20, a3 # flag_intRxStart
-	mv 		x21, a4 # flag_intRxEnd
-	mv 		x22, x0
+	li	 	x16, SYS_SEND_DATA
+	beq	 	 a0, x16, send_data_func
 
-	#lui 	x23, %hi(_rv32i_plic_handle)
-	#lw		x24, %lo(_rv32i_plic_handle)(x23)
+	li		x16, SYS_SET_RECV_INFO
+	beq		 a0, x16, set_recv_info_func
+
+10: j		10b	//死循环，输入错误的功能号
+	ret			//心理安慰，并不会返回
 	
-	la		x24, _rv32i_plic_handle
+
+//初始化系统，输入必要的地址信息，返回中断程序的地址
+//a1, plic_claim的地址, 其实也可以不用传送
+init_system_func:
+	mv		REG_plic_claim, a1 # plic_claim
+
+	/*初始化isr_hdl_table，中断表*/
+	la		x16, isr_hdl_table
 	
-	li		x25, 1
-	li		x26, 0
-	li		x27, 0
-	li		x28, CDR_INT_TXEND
-	li		x29, CDR_INT_RXERROR
-	li		x30, CDR_INT_RXSTART
-	li		x31, CDR_INT_RXEND
+	la		x17, isr_tx0_end_hdl
+	addi	x16, x16, 4
+	sw		x17, 0(x16)
 
+	la		x17, isr_tx1_end_hdl
+	addi	x16, x16, 4
+	sw		x17, 0(x16)
 
-    mv		a0, x24
+	la		x17, isr_rx0_err_hdl
+	addi	x16, x16, 4
+	sw		x17, 0(x16)
 
-	li		x23, 0
-	li		x24, 0
+	la 		x17, isr_rx1_err_hdl
+	addi	x16, x16, 4
+	sw		x17, 0(x16)
+
+	la		x17, isr_rx0_start_hdl
+	addi	x16, x16, 4
+	sw		x17, 0(x16)
+
+	la		x17, isr_rx1_start_hdl
+	addi	x16, x16, 4
+	sw		x17, 0(x16)
+
+	la		x17, isr_rx0_end_hdl
+	addi	x16, x16, 4
+	sw		x17, 0(x16)
+
+	la		x17, isr_rx1_end_hdl
+	addi	x16, x16, 4
+	sw		x17, 0(x16)
+
+	la		x17, isr_tx0_deq_hdl
+	addi	x16, x16, 4
+	sw		x17, 0(x16)
+
+	la		x17, isr_tx1_deq_hdl
+	addi	x16, x16, 4
+	sw		x17, 0(x16)
+
+	la		x17, isr_rx0_enq_hdl
+	addi	x16, x16, 4
+	sw		x17, 0(x16)
+
+	la		x17, isr_rx1_enq_hdl
+	addi	x16, x16, 4
+	sw		x17, 0(x16)
+
+	la		x17, _rv32i_plic_handle
+
+    mv		a0, x17
+
+	li		REG_TL2CDR_BASE, 	TL2CDR_BASE
+	la		REG_ISR_ADDR, 		isr_hdl_table
+	li		REG_min_isr_num, 	14
+	li		REG_max_isr_num, 	25
+	li		x23,				4
     ret
 
+//主站启动发送数据
+//a1, 当前需要发送的数据的地址
+//a2, 当前数据发送的长度
+send_data_func:
+	mv		REG_tx_data, 	 a1
+	mv 		REG_tx_data_len, a2
+
+//*tx0_txLen = 8 + tx_len;  //前导+长度命令
+	mv		x16, a2
+	addi	x17, x16, 8
+	sw		x17, TX0_WriteTxLen(REG_TL2CDR_BASE)
+
+//*tx0_txFifo = (tx_len << 20) | (0 << 16) | 0x0000;
+	slli	x17, x16, 20
+	sw		x17, TX0_WriteTxFifo(REG_TL2CDR_BASE)
+
+//*tx0_txFifo = data[0]
+	lw		x17, 0(REG_tx_data)
+	sw		x17, TX0_WriteTxFifo(REG_TL2CDR_BASE)
+
+	//li		x16, 4
+	add		REG_tx_data, REG_tx_data, x23
+	sub		REG_tx_data_len, REG_tx_data_len, x23
+	
+	li		a0,  1
+	ret
+
+//设置接收数据的地址,第一个接收数据的长度，往后都是数据
+//a1, 设置接收数据的缓冲区
+set_recv_info_func:
+	mv		REG_rx_data, 	a1
+	li		a0, 1
+	ret
+
+//--------------------------------------------
+//这是中断程序开始的地方
+
 	.balign 32
 _rv32i_plic_handle:
-	lw 		x23, 0(x17)    			# x23 = *plic_claim
-	sw  	x23, 0(x17)				# *plic_claim = x23
+	lw 		x16, 0(REG_plic_claim)    			# x16 = *plic_claim
+	sw  	x16, 0(REG_plic_claim)				# *plic_claim = x16
 
-	#li 		x25, 1
-#if 0
-	li		x24, CDR_INT_TXEND
-	bne 	x23, x24, 1f   			#_if (x23 != x24) goto 1f
-	sw		x25, 0(x18)				#_else
-	j 		4f
+	bltu	x16, REG_min_isr_num, exit_handle	#if x16 < REG_min_isr_num then goto exit_handle
+	bltu	REG_max_isr_num, x16, exit_handle	#if REG_max_isr_num < x16 then goto exit_handle
+	sub 	x17, x16, REG_min_isr_num
+	slli	x17, x17, 2							# x17 = x17 * 4
+	add		x18, REG_ISR_ADDR, x17				# x18 = REG_ISR_ADDR + x17
+	jr		x18
 
-1:
-	li  	x24, CDR_INT_RXERROR
-	bne 	x23, x24, 2f   			#_if (x23 != x24) goto 2f
-	sw		x25, 0(x19)				#_else
-	j 		4f
-
-2:
-	li  	x24, CDR_INT_RXSTART
-	bne 	x23, x24, 3f			#_if (x23 != x24) goto 3f
-	sw		x25, 0(x20)				#_else
-	j 		4f
-
-3:
-	li  	x24, CDR_INT_RXEND
-	bne 	x23, x24, 4f			#_if (x23 != x24) goto 4f
-	sw		x25, 0(x21)				#_else
-#else
-
-
-
-	bne 	x23, x28, 1f   			#_if (x23 != x24) goto 1f
-	sw		x25, 0(x18)				#_else
-	j 		4f
-
-1:
-	bne 	x23, x29, 2f   			#_if (x23 != x24) goto 2f
-	sw		x25, 0(x19)				#_else
-	j 		4f
-
-2:
-	bne 	x23, x30, 3f			#_if (x23 != x24) goto 3f
-	sw		x25, 0(x20)				#_else
-	j 		4f
-
-3:
-	bne 	x23, x31, 4f			#_if (x23 != x24) goto 4f
-	sw		x25, 0(x21)				#_else
-
-
-#endif
-
-4:
+exit_handle:
 	mret
+
+isr_tx0_end_hdl:
+	mret
+
+isr_tx1_end_hdl:
+	mret
+
+isr_rx0_err_hdl:
+	mret
+
+isr_rx1_err_hdl:
+	mret
+
+isr_rx0_start_hdl:
+	mret
+
+isr_rx1_start_hdl:
+	lw		x22, RX1_ReadRxLen(REG_TL2CDR_BASE)
+	sw		x22, 0(REG_rx_data)
+	add		REG_rx_data, REG_rx_data, x23
+	mret
+
+isr_rx0_end_hdl:
+	mret
+
+isr_rx1_end_hdl:
+	mret
+
+isr_tx0_deq_hdl:
+	bgtz	REG_tx_data_len, 1f //if (REG_tx_data_len > 0)
+	lw		x17, 0(REG_tx_data)
+	sw		x17, TX0_WriteTxFifo(REG_TL2CDR_BASE)
+
+	//li		x16, 4
+	add		REG_tx_data, REG_tx_data, x23
+	sub		REG_tx_data_len, REG_tx_data_len, x23
+1:
+	mret
+
+isr_tx1_deq_hdl:
+	mret
+
+isr_rx0_enq_hdl:
+	lw		x17, RX1_ReadRxFifo(REG_TL2CDR_BASE)
+	sw		x17, 0(REG_rx_data)
+	add		REG_rx_data, REG_rx_data, x23
+	mret
+
+isr_rx1_enq_hdl:
+	mret
+
+	.balign 4
+isr_hdl_table:
+	.space 64
+
+	nop
\ No newline at end of file
diff --git a/tb/sw/src/sysDef.h b/tb/sw/src/sysDef.h
new file mode 100644
index 0000000..c9ec834
--- /dev/null
+++ b/tb/sw/src/sysDef.h
@@ -0,0 +1,10 @@
+#ifndef __SYSDEF_H__
+#define __SYSDEF_H__
+
+#define SYS_INIT			0
+#define SYS_SEND_DATA		1
+#define SYS_SET_RECV_INFO	2
+
+
+#endif
+
diff --git a/tb/sw/tl2cdr/tl2cdr.c b/tb/sw/tl2cdr/tl2cdr.c
index d7cccb1..6362d25 100644
--- a/tb/sw/tl2cdr/tl2cdr.c
+++ b/tb/sw/tl2cdr/tl2cdr.c
@@ -5,6 +5,7 @@
 #error TL2CDR Base address not define!!!
 #endif
 
+#ifdef OLD_CODE
 volatile uint32_t * const cdr_status = (uint32_t*)( TL2CDR_BASE + CDR_ReadStatus ); //read
 volatile uint32_t * const cdr_txLen  = (uint32_t*)( TL2CDR_BASE + CDR_WriteTxLen ); //write
 volatile uint32_t * const cdr_txFifo = (uint32_t*)( TL2CDR_BASE + CDR_WriteTxFifo ); //write
@@ -17,93 +18,32 @@ volatile uint32_t * const cdr_rxFifo    = (uint32_t*)( TL2CDR_BASE + CDR_ReadRxF
 volatile uint32_t * const cdr_IsLast    = (uint32_t*)( TL2CDR_BASE + CDR_ReadIsLast ); //read
 volatile uint32_t * const cdr_rxCrc     = (uint32_t*)( TL2CDR_BASE + CDR_ReadRxCrc );
 volatile uint32_t * const cdr_txCrc     = (uint32_t*)( TL2CDR_BASE + CDR_ReadTxCrc);
-
-
-#if 0
-void cdr_set_downStream(){
-	*cdr_softReset = 1; //复位脉冲
-	*cdr_direct = 0;
-}
-
-void cdr_set_upStream(){
-	*cdr_softReset = 1; //复位脉冲
-	*cdr_direct = 1;
-}
-
-
-void cdr_simple_tx( uint32_t txLen, uint8_t operator, uint8_t* data){
-	//发送下行包头
-	assert(txLen < 2^12);
-	assert(txLen > 8 );
-	assert(txLen % 4 == 0 );
-	assert(operator < 2^4);
-
-	*cdr_txLen = txLen;
-	*cdr_txFifo = (uint32_t)( txLen << 20) | ( operator << 16) | 0x0000;
-	*cdr_txFifo = (uint32_t)0x00;
-
-	for( uint32_t i = 0; i < (txLen-8)/4; i ++ ){
-		*cdr_txFifo = data[4*i+3]<< 24 | data[4*i+2]<<16 | data[4*i+1]<< 8 | data[4*i+0] << 0;
-	}
-
-
-
-}
-
-
-uint32_t cdr_wait_tx_finish(){
-	// //等待发送完成标志
-	// asm volatile (
-	// 	"1:\n"
-	// 	"andi %0, sp, 0x01\n"
-	// 	"beqz %0, 1b\n"
-	// 	"andi sp, sp, 0xFE\n"
-	// 	:"+r"(flag)
-	// );	
-}
-
-uint32_t cdr_wait_rx_start(){
-	//接收第一个包
-	asm volatile (
-		"1:\n"
-		"andi %0, sp, 0x04\n"
-		"beqz %0, 1b\n"
-		"andi sp, sp, 0xFB\n"
-		:"+r"(flag)
-	);	
-}
-
-uint32_t cdr_check_rx_fail(){
-
-}
-
-void cdr_simple_rx(uint32_t* rxLen, uint8_t* operator, uint8_t* data){
-
-
-	uint32_t readDat;
-
-	readDat = *cdr_rxFifo;	
-	*operator = (readDat >> 16) & 0xf;
-	*rxLen    = readDat >> 20;
-	readDat = *cdr_rxFifo;
-
-	for( uint32_t i = 0; i < ( *rxLen >> 2); i ++ ){ //一次传4byte
-		readDat = *cdr_rxFifo;
-		data[4*i+1] = (uint8_t)( (readDat >>  0) & 0xFF);
-		data[4*i+0] = (uint8_t)( (readDat >>  8) & 0xFF);
-		data[4*i+2] = (uint8_t)( (readDat >> 16) & 0xFF);
-		data[4*i+3] = (uint8_t)( (readDat >> 24) & 0xFF);
-	}
-
-	//CRC
-	uint32_t crc = *cdr_rxFifo; //CRC
-
-}
-
-
-void cdr_slave_function(){
-	
-}
-
 #endif
 
+
+volatile uint32_t * const tx0_softReset  = (uint32_t*)( TL2CDR_BASE + TX0_WriteSoftReset );
+volatile uint32_t * const tx0_txLen      = (uint32_t*)( TL2CDR_BASE + TX0_WriteTxLen );
+volatile uint32_t * const tx0_txFifo     = (uint32_t*)( TL2CDR_BASE + TX0_WriteTxFifo );
+volatile uint32_t * const tx0_txCrc      = (uint32_t*)( TL2CDR_BASE + TX0_ReadTxCrc );
+
+volatile uint32_t * const tx1_softReset  = (uint32_t*)( TL2CDR_BASE + TX1_WriteSoftReset );
+volatile uint32_t * const tx1_txLen      = (uint32_t*)( TL2CDR_BASE + TX1_WriteTxLen );
+volatile uint32_t * const tx1_txFifo     = (uint32_t*)( TL2CDR_BASE + TX1_WriteTxFifo );
+volatile uint32_t * const tx1_txCrc      = (uint32_t*)( TL2CDR_BASE + TX1_ReadTxCrc );
+
+volatile uint32_t * const rx0_softReset  = (uint32_t*)( TL2CDR_BASE + RX0_WriteSoftReset );
+volatile uint32_t * const rx0_rxLen      = (uint32_t*)( TL2CDR_BASE + RX0_ReadRxLen );
+volatile uint32_t * const rx0_rxFifo     = (uint32_t*)( TL2CDR_BASE + RX0_ReadRxFifo );
+volatile uint32_t * const rx0_rxCrc      = (uint32_t*)( TL2CDR_BASE + RX0_ReadRxCrc );
+volatile uint32_t * const rx0_rxTimerAim = (uint32_t*)( TL2CDR_BASE + RX0_WrtieLimitTimerAim );
+volatile uint32_t * const rx0_rxTxPair   = (uint32_t*)( TL2CDR_BASE + RX0_WriteLimitTxPair );
+
+volatile uint32_t * const rx1_softReset  = (uint32_t*)( TL2CDR_BASE + RX1_WriteSoftReset );
+volatile uint32_t * const rx1_rxLen      = (uint32_t*)( TL2CDR_BASE + RX1_ReadRxLen );
+volatile uint32_t * const rx1_rxFifo     = (uint32_t*)( TL2CDR_BASE + RX1_ReadRxFifo );
+volatile uint32_t * const rx1_rxCrc      = (uint32_t*)( TL2CDR_BASE + RX1_ReadRxCrc );
+volatile uint32_t * const rx1_rxTimerAim = (uint32_t*)( TL2CDR_BASE + RX1_WrtieLimitTimerAim );
+volatile uint32_t * const rx1_rxTxPair   = (uint32_t*)( TL2CDR_BASE + RX1_WriteLimitTxPair );
+
+volatile uint32_t * const HLM_status     = (uint32_t*)( TL2CDR_BASE + HLM_ReadStatus );
+volatile uint32_t * const HLM_isLast     = (uint32_t*)( TL2CDR_BASE + HLM_ReadIsLast );
diff --git a/tb/sw/tl2cdr/tl2cdr.h b/tb/sw/tl2cdr/tl2cdr.h
index 18d730c..29f1f98 100644
--- a/tb/sw/tl2cdr/tl2cdr.h
+++ b/tb/sw/tl2cdr/tl2cdr.h
@@ -5,50 +5,113 @@
 #include <stdint.h>
 #endif
 
-#define TL2CDR_BASE 0x10000000U
+#define TL2CDR_BASE             0x10000000U
 
 
-// volatile uint32_t *cdr_status = (uint32_t*)( 0x000 + 0x0 ); //read
-// volatile uint32_t *cdr_txLen  = (uint32_t*)( 0x000 + 0x4 ); //write
-// volatile uint32_t *cdr_txFifo = (uint32_t*)( 0x000 + 0x8 ); //write
-// volatile uint32_t *cdr_direct = (uint32_t*)( 0x000 + 0xc ); //write
+#define OLD_CODE
+#ifdef OLD_CODE
+#define CDR_ReadStatus          0x00U
+#define CDR_WriteTxLen          0x04U
+#define CDR_WriteTxFifo         0x08U
+#define CDR_WriteTransDir       0x0cU
+#define CDR_WriteSoftReset      0x10U
+#define CDR_ReadRxLen           0x18U
+#define CDR_ReadRxFifo          0x1cU
+#define CDR_ReadIsLast          0x20U
+#define CDR_ReadTxCrc           0x24U
+#define CDR_ReadRxCrc           0x28U
+#define CDR_WriteLimitTimer     0x2cU
 
-// volatile uint32_t *cdr_softReset = (uint32_t*)( 0x000 + 0x10 ); //write
-// volatile uint32_t *cdr_rxLen     = (uint32_t*)( 0x000 + 0x18 ); //read
-// volatile uint32_t *cdr_rxFifo    = (uint32_t*)( 0x000 + 0x1c ); //read
+#define CDR_INT_TXEND           14U
+#define CDR_INT_RXERROR         15U
+#define CDR_INT_RXSTART         16U
+#define CDR_INT_RXEND           17U
+#endif
 
-#define CDR_ReadStatus     0x00
-#define CDR_WriteTxLen     0x04
-#define CDR_WriteTxFifo    0x08
-#define CDR_WriteTransDir  0x0c
-#define CDR_WriteSoftReset 0x10
-#define CDR_ReadRxLen      0x18
-#define CDR_ReadRxFifo     0x1c
-#define CDR_ReadIsLast     0x20
-#define CDR_ReadTxCrc      0x24
-#define CDR_ReadRxCrc      0x28
-#define CDR_WriteLimitTimer 0x2c
 
-#define CDR_INT_TXEND   14
-#define CDR_INT_RXERROR 15
-#define CDR_INT_RXSTART 16
-#define CDR_INT_RXEND   17
+#define CDR_INT_TX0END          14U
+#define CDR_INT_TX1END          15U
+#define CDR_INT_RX0ERROR        16U
+#define CDR_INT_RX1ERROR        17U
+#define CDR_INT_RX0START        18U
+#define CDR_INT_RX1START        19U
+#define CDR_INT_RX0END          20U
+#define CDR_INT_RX1END          21U
+#define CDR_INT_TX0_FIFO_DEQ    22U          
+#define CDR_INT_TX1_FIFO_DEQ    23U
+#define CDR_INT_RX0_FIFO_ENQ    24U
+#define CDR_INT_RX1_FIFO_ENQ    25U
+
+
+
+#define TX0_WriteSoftReset      0x00U
+#define TX0_WriteTxLen          0x04U
+#define TX0_WriteTxFifo         0x08U
+#define TX0_ReadTxCrc           0x0CU
+
+#define TX1_WriteSoftReset      0x10U
+#define TX1_WriteTxLen          0x14U
+#define TX1_WriteTxFifo         0x18U
+#define TX1_ReadTxCrc           0x1CU
+
+#define RX0_WriteSoftReset      0x20U
+#define RX0_ReadRxLen           0x24U
+#define RX0_ReadRxFifo          0x28U
+#define RX0_ReadRxCrc           0x2CU
+#define RX0_WrtieLimitTimerAim  0x30U
+#define RX0_WriteLimitTxPair    0x34U
+
+#define RX1_WriteSoftReset      0x40U
+#define RX1_ReadRxLen           0x44U
+#define RX1_ReadRxFifo          0x48U
+#define RX1_ReadRxCrc           0x4CU
+#define RX1_WrtieLimitTimerAim  0x50U
+#define RX1_WriteLimitTxPair    0x54U
+
+#define HLM_ReadStatus          0x58U
+#define HLM_ReadIsLast          0x5CU
+
 
 #ifndef __ASSEMBLER__
-extern volatile uint32_t * const cdr_status;// = (uint32_t*)( TL2CDR_BASE + CDR_ReadStatus ); //read
-extern volatile uint32_t * const cdr_txLen;//  = (uint32_t*)( TL2CDR_BASE + CDR_WriteTxLen ); //write
-extern volatile uint32_t * const cdr_txFifo;// = (uint32_t*)( TL2CDR_BASE + CDR_WriteTxFifo ); //write
-extern volatile uint32_t * const cdr_direct;// = (uint32_t*)( TL2CDR_BASE + CDR_WriteTransDir ); //write
-extern volatile uint32_t * const cdr_softReset;// = (uint32_t*)( TL2CDR_BASE + CDR_WriteSoftReset ); //write
-extern volatile uint32_t * const cdr_rxLen;//     = (uint32_t*)( TL2CDR_BASE + CDR_ReadRxLen ); //read
-extern volatile uint32_t * const cdr_rxFifo;//    = (uint32_t*)( TL2CDR_BASE + CDR_ReadRxFifo ); //read
-extern volatile uint32_t * const cdr_IsLast;//    = (uint32_t*)( TL2CDR_BASE + CDR_ReadIsLast ); //read
-extern volatile uint32_t * const cdr_rxCrc;//     = (uint32_t*)( TL2CDR_BASE + CDR_ReadRxCrc );
-extern volatile uint32_t * const cdr_txCrc;//     = (uint32_t*)( TL2CDR_BASE + CDR_ReadTxCrc);
-// extern uint8_t gpio_read();
-// extern uint32_t gpio_write( uint32_t data );
+#ifdef OLD_CODE
+extern volatile uint32_t * const cdr_status;
+extern volatile uint32_t * const cdr_txLen;
+extern volatile uint32_t * const cdr_txFifo;
+extern volatile uint32_t * const cdr_direct;
+extern volatile uint32_t * const cdr_softReset;
+extern volatile uint32_t * const cdr_rxLen;
+extern volatile uint32_t * const cdr_rxFifo;
+extern volatile uint32_t * const cdr_IsLast;
+extern volatile uint32_t * const cdr_rxCrc;
+extern volatile uint32_t * const cdr_txCrc;
+#endif
 
-// void gpio_test();
+extern volatile uint32_t * const tx0_softReset;
+extern volatile uint32_t * const tx0_txLen;
+extern volatile uint32_t * const tx0_txFifo;
+extern volatile uint32_t * const tx0_txCrc;
+
+extern volatile uint32_t * const tx1_softReset;
+extern volatile uint32_t * const tx1_txLen;
+extern volatile uint32_t * const tx1_txFifo;
+extern volatile uint32_t * const tx1_txCrc;
+
+extern volatile uint32_t * const rx0_softReset;
+extern volatile uint32_t * const rx0_rxLen;
+extern volatile uint32_t * const rx0_rxFifo;
+extern volatile uint32_t * const rx0_rxCrc;
+extern volatile uint32_t * const rx0_rxTimerAim;
+extern volatile uint32_t * const rx0_rxTxPair;
+
+extern volatile uint32_t * const rx1_softReset;
+extern volatile uint32_t * const rx1_rxLen;
+extern volatile uint32_t * const rx1_rxFifo;
+extern volatile uint32_t * const rx1_rxCrc;
+extern volatile uint32_t * const rx1_rxTimerAim;
+extern volatile uint32_t * const rx1_rxTxPair;
+
+extern volatile uint32_t * const HLM_status;
+extern volatile uint32_t * const HLM_isLast;
 #endif
 
 #endif