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@@ -5,6 +5,7 @@
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#error TL2CDR Base address not define!!!
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#endif
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#ifdef OLD_CODE
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volatile uint32_t * const cdr_status = (uint32_t*)( TL2CDR_BASE + CDR_ReadStatus ); //read
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volatile uint32_t * const cdr_txLen = (uint32_t*)( TL2CDR_BASE + CDR_WriteTxLen ); //write
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volatile uint32_t * const cdr_txFifo = (uint32_t*)( TL2CDR_BASE + CDR_WriteTxFifo ); //write
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@@ -17,93 +18,32 @@ volatile uint32_t * const cdr_rxFifo = (uint32_t*)( TL2CDR_BASE + CDR_ReadRxF
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volatile uint32_t * const cdr_IsLast = (uint32_t*)( TL2CDR_BASE + CDR_ReadIsLast ); //read
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volatile uint32_t * const cdr_rxCrc = (uint32_t*)( TL2CDR_BASE + CDR_ReadRxCrc );
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volatile uint32_t * const cdr_txCrc = (uint32_t*)( TL2CDR_BASE + CDR_ReadTxCrc);
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#if 0
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void cdr_set_downStream(){
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*cdr_softReset = 1; //复位脉冲
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*cdr_direct = 0;
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}
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void cdr_set_upStream(){
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*cdr_softReset = 1; //复位脉冲
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*cdr_direct = 1;
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}
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void cdr_simple_tx( uint32_t txLen, uint8_t operator, uint8_t* data){
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//发送下行包头
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assert(txLen < 2^12);
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assert(txLen > 8 );
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assert(txLen % 4 == 0 );
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assert(operator < 2^4);
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*cdr_txLen = txLen;
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*cdr_txFifo = (uint32_t)( txLen << 20) | ( operator << 16) | 0x0000;
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*cdr_txFifo = (uint32_t)0x00;
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for( uint32_t i = 0; i < (txLen-8)/4; i ++ ){
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*cdr_txFifo = data[4*i+3]<< 24 | data[4*i+2]<<16 | data[4*i+1]<< 8 | data[4*i+0] << 0;
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}
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}
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uint32_t cdr_wait_tx_finish(){
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// //等待发送完成标志
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// asm volatile (
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// "1:\n"
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// "andi %0, sp, 0x01\n"
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// "beqz %0, 1b\n"
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// "andi sp, sp, 0xFE\n"
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// :"+r"(flag)
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// );
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}
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uint32_t cdr_wait_rx_start(){
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//接收第一个包
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asm volatile (
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"1:\n"
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"andi %0, sp, 0x04\n"
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"beqz %0, 1b\n"
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"andi sp, sp, 0xFB\n"
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:"+r"(flag)
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);
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}
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uint32_t cdr_check_rx_fail(){
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}
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void cdr_simple_rx(uint32_t* rxLen, uint8_t* operator, uint8_t* data){
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uint32_t readDat;
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readDat = *cdr_rxFifo;
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*operator = (readDat >> 16) & 0xf;
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*rxLen = readDat >> 20;
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readDat = *cdr_rxFifo;
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for( uint32_t i = 0; i < ( *rxLen >> 2); i ++ ){ //一次传4byte
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readDat = *cdr_rxFifo;
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data[4*i+1] = (uint8_t)( (readDat >> 0) & 0xFF);
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data[4*i+0] = (uint8_t)( (readDat >> 8) & 0xFF);
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data[4*i+2] = (uint8_t)( (readDat >> 16) & 0xFF);
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data[4*i+3] = (uint8_t)( (readDat >> 24) & 0xFF);
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}
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//CRC
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uint32_t crc = *cdr_rxFifo; //CRC
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}
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void cdr_slave_function(){
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}
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#endif
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volatile uint32_t * const tx0_softReset = (uint32_t*)( TL2CDR_BASE + TX0_WriteSoftReset );
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volatile uint32_t * const tx0_txLen = (uint32_t*)( TL2CDR_BASE + TX0_WriteTxLen );
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volatile uint32_t * const tx0_txFifo = (uint32_t*)( TL2CDR_BASE + TX0_WriteTxFifo );
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volatile uint32_t * const tx0_txCrc = (uint32_t*)( TL2CDR_BASE + TX0_ReadTxCrc );
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volatile uint32_t * const tx1_softReset = (uint32_t*)( TL2CDR_BASE + TX1_WriteSoftReset );
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volatile uint32_t * const tx1_txLen = (uint32_t*)( TL2CDR_BASE + TX1_WriteTxLen );
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volatile uint32_t * const tx1_txFifo = (uint32_t*)( TL2CDR_BASE + TX1_WriteTxFifo );
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volatile uint32_t * const tx1_txCrc = (uint32_t*)( TL2CDR_BASE + TX1_ReadTxCrc );
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volatile uint32_t * const rx0_softReset = (uint32_t*)( TL2CDR_BASE + RX0_WriteSoftReset );
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volatile uint32_t * const rx0_rxLen = (uint32_t*)( TL2CDR_BASE + RX0_ReadRxLen );
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volatile uint32_t * const rx0_rxFifo = (uint32_t*)( TL2CDR_BASE + RX0_ReadRxFifo );
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volatile uint32_t * const rx0_rxCrc = (uint32_t*)( TL2CDR_BASE + RX0_ReadRxCrc );
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volatile uint32_t * const rx0_rxTimerAim = (uint32_t*)( TL2CDR_BASE + RX0_WrtieLimitTimerAim );
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volatile uint32_t * const rx0_rxTxPair = (uint32_t*)( TL2CDR_BASE + RX0_WriteLimitTxPair );
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volatile uint32_t * const rx1_softReset = (uint32_t*)( TL2CDR_BASE + RX1_WriteSoftReset );
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volatile uint32_t * const rx1_rxLen = (uint32_t*)( TL2CDR_BASE + RX1_ReadRxLen );
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volatile uint32_t * const rx1_rxFifo = (uint32_t*)( TL2CDR_BASE + RX1_ReadRxFifo );
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volatile uint32_t * const rx1_rxCrc = (uint32_t*)( TL2CDR_BASE + RX1_ReadRxCrc );
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volatile uint32_t * const rx1_rxTimerAim = (uint32_t*)( TL2CDR_BASE + RX1_WrtieLimitTimerAim );
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volatile uint32_t * const rx1_rxTxPair = (uint32_t*)( TL2CDR_BASE + RX1_WriteLimitTxPair );
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volatile uint32_t * const HLM_status = (uint32_t*)( TL2CDR_BASE + HLM_ReadStatus );
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volatile uint32_t * const HLM_isLast = (uint32_t*)( TL2CDR_BASE + HLM_ReadIsLast );
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@@ -5,50 +5,113 @@
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#include <stdint.h>
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#endif
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#define TL2CDR_BASE 0x10000000U
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#define TL2CDR_BASE 0x10000000U
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// volatile uint32_t *cdr_status = (uint32_t*)( 0x000 + 0x0 ); //read
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// volatile uint32_t *cdr_txLen = (uint32_t*)( 0x000 + 0x4 ); //write
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// volatile uint32_t *cdr_txFifo = (uint32_t*)( 0x000 + 0x8 ); //write
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// volatile uint32_t *cdr_direct = (uint32_t*)( 0x000 + 0xc ); //write
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#define OLD_CODE
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#ifdef OLD_CODE
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#define CDR_ReadStatus 0x00U
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#define CDR_WriteTxLen 0x04U
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#define CDR_WriteTxFifo 0x08U
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#define CDR_WriteTransDir 0x0cU
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#define CDR_WriteSoftReset 0x10U
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#define CDR_ReadRxLen 0x18U
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#define CDR_ReadRxFifo 0x1cU
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#define CDR_ReadIsLast 0x20U
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#define CDR_ReadTxCrc 0x24U
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#define CDR_ReadRxCrc 0x28U
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#define CDR_WriteLimitTimer 0x2cU
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// volatile uint32_t *cdr_softReset = (uint32_t*)( 0x000 + 0x10 ); //write
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// volatile uint32_t *cdr_rxLen = (uint32_t*)( 0x000 + 0x18 ); //read
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// volatile uint32_t *cdr_rxFifo = (uint32_t*)( 0x000 + 0x1c ); //read
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#define CDR_INT_TXEND 14U
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#define CDR_INT_RXERROR 15U
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#define CDR_INT_RXSTART 16U
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#define CDR_INT_RXEND 17U
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#endif
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#define CDR_ReadStatus 0x00
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#define CDR_WriteTxLen 0x04
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#define CDR_WriteTxFifo 0x08
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#define CDR_WriteTransDir 0x0c
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#define CDR_WriteSoftReset 0x10
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#define CDR_ReadRxLen 0x18
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#define CDR_ReadRxFifo 0x1c
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#define CDR_ReadIsLast 0x20
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#define CDR_ReadTxCrc 0x24
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#define CDR_ReadRxCrc 0x28
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#define CDR_WriteLimitTimer 0x2c
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#define CDR_INT_TXEND 14
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#define CDR_INT_RXERROR 15
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#define CDR_INT_RXSTART 16
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#define CDR_INT_RXEND 17
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#define CDR_INT_TX0END 14U
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#define CDR_INT_TX1END 15U
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#define CDR_INT_RX0ERROR 16U
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#define CDR_INT_RX1ERROR 17U
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#define CDR_INT_RX0START 18U
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#define CDR_INT_RX1START 19U
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#define CDR_INT_RX0END 20U
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#define CDR_INT_RX1END 21U
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#define CDR_INT_TX0_FIFO_DEQ 22U
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#define CDR_INT_TX1_FIFO_DEQ 23U
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#define CDR_INT_RX0_FIFO_ENQ 24U
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#define CDR_INT_RX1_FIFO_ENQ 25U
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#define TX0_WriteSoftReset 0x00U
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#define TX0_WriteTxLen 0x04U
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#define TX0_WriteTxFifo 0x08U
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#define TX0_ReadTxCrc 0x0CU
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#define TX1_WriteSoftReset 0x10U
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#define TX1_WriteTxLen 0x14U
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#define TX1_WriteTxFifo 0x18U
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#define TX1_ReadTxCrc 0x1CU
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#define RX0_WriteSoftReset 0x20U
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#define RX0_ReadRxLen 0x24U
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#define RX0_ReadRxFifo 0x28U
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#define RX0_ReadRxCrc 0x2CU
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#define RX0_WrtieLimitTimerAim 0x30U
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#define RX0_WriteLimitTxPair 0x34U
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#define RX1_WriteSoftReset 0x40U
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#define RX1_ReadRxLen 0x44U
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#define RX1_ReadRxFifo 0x48U
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#define RX1_ReadRxCrc 0x4CU
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#define RX1_WrtieLimitTimerAim 0x50U
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#define RX1_WriteLimitTxPair 0x54U
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#define HLM_ReadStatus 0x58U
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#define HLM_ReadIsLast 0x5CU
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#ifndef __ASSEMBLER__
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extern volatile uint32_t * const cdr_status;// = (uint32_t*)( TL2CDR_BASE + CDR_ReadStatus ); //read
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extern volatile uint32_t * const cdr_txLen;// = (uint32_t*)( TL2CDR_BASE + CDR_WriteTxLen ); //write
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extern volatile uint32_t * const cdr_txFifo;// = (uint32_t*)( TL2CDR_BASE + CDR_WriteTxFifo ); //write
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extern volatile uint32_t * const cdr_direct;// = (uint32_t*)( TL2CDR_BASE + CDR_WriteTransDir ); //write
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extern volatile uint32_t * const cdr_softReset;// = (uint32_t*)( TL2CDR_BASE + CDR_WriteSoftReset ); //write
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extern volatile uint32_t * const cdr_rxLen;// = (uint32_t*)( TL2CDR_BASE + CDR_ReadRxLen ); //read
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extern volatile uint32_t * const cdr_rxFifo;// = (uint32_t*)( TL2CDR_BASE + CDR_ReadRxFifo ); //read
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extern volatile uint32_t * const cdr_IsLast;// = (uint32_t*)( TL2CDR_BASE + CDR_ReadIsLast ); //read
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extern volatile uint32_t * const cdr_rxCrc;// = (uint32_t*)( TL2CDR_BASE + CDR_ReadRxCrc );
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extern volatile uint32_t * const cdr_txCrc;// = (uint32_t*)( TL2CDR_BASE + CDR_ReadTxCrc);
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// extern uint8_t gpio_read();
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// extern uint32_t gpio_write( uint32_t data );
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#ifdef OLD_CODE
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extern volatile uint32_t * const cdr_status;
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extern volatile uint32_t * const cdr_txLen;
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extern volatile uint32_t * const cdr_txFifo;
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extern volatile uint32_t * const cdr_direct;
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extern volatile uint32_t * const cdr_softReset;
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extern volatile uint32_t * const cdr_rxLen;
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extern volatile uint32_t * const cdr_rxFifo;
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extern volatile uint32_t * const cdr_IsLast;
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extern volatile uint32_t * const cdr_rxCrc;
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extern volatile uint32_t * const cdr_txCrc;
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#endif
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// void gpio_test();
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extern volatile uint32_t * const tx0_softReset;
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extern volatile uint32_t * const tx0_txLen;
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extern volatile uint32_t * const tx0_txFifo;
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extern volatile uint32_t * const tx0_txCrc;
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extern volatile uint32_t * const tx1_softReset;
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extern volatile uint32_t * const tx1_txLen;
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extern volatile uint32_t * const tx1_txFifo;
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extern volatile uint32_t * const tx1_txCrc;
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extern volatile uint32_t * const rx0_softReset;
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extern volatile uint32_t * const rx0_rxLen;
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extern volatile uint32_t * const rx0_rxFifo;
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extern volatile uint32_t * const rx0_rxCrc;
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extern volatile uint32_t * const rx0_rxTimerAim;
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extern volatile uint32_t * const rx0_rxTxPair;
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extern volatile uint32_t * const rx1_softReset;
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extern volatile uint32_t * const rx1_rxLen;
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extern volatile uint32_t * const rx1_rxFifo;
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extern volatile uint32_t * const rx1_rxCrc;
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extern volatile uint32_t * const rx1_rxTimerAim;
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extern volatile uint32_t * const rx1_rxTxPair;
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extern volatile uint32_t * const HLM_status;
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extern volatile uint32_t * const HLM_isLast;
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#endif
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#endif
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