SM除错使用commit指针策略，需要测试覆盖1）一个包中同时写入操作0~4个sm的1~4个元素后出错，是否对后续SM操作发生影响，2）尝试在SM空时读，尝试在SM满时写，是否会对后续提交操作产生影响 3）寄存器0x538记录的时间不会区分是否是错误包4）在前述多次复杂操作后寄存器0x301的计数是否正常 5）从spi侧写入是否正常 6）主站写入的包错误将不会判断

src/main/scala/backBoard/shin/MstSlvSwitch.scala

@@ -120,13 +120,24 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{
 
   val lvdsSMEnq = for( i <- 0 until 4 ) yield WireDefault(false.B); interface.io.lvdsSMEnq := lvdsSMEnq
   val lvdsSMDeq = for( i <- 0 until 4 ) yield WireDefault(false.B); interface.io.lvdsSMDeq := lvdsSMDeq
-
+  val lvdsSMComf = for( i <- 0 until 4 ) yield WireDefault(false.B)
+  val lvdsSMAbrt = for( i <- 0 until 4 ) yield WireDefault(false.B)
 
   smUnit(0).io.enq := lvdsSMEnq(0)
   smUnit(2).io.enq := lvdsSMEnq(1)
   smUnit(4).io.enq := lvdsSMEnq(2)
   smUnit(6).io.enq := lvdsSMEnq(3)
 
+  smUnit(0).io.isComf := lvdsSMComf(0)
+  smUnit(2).io.isComf := lvdsSMComf(1)
+  smUnit(4).io.isComf := lvdsSMComf(2)
+  smUnit(6).io.isComf := lvdsSMComf(3)
+
+  smUnit(0).io.isAbrt := lvdsSMAbrt(0)
+  smUnit(2).io.isAbrt := lvdsSMAbrt(1)
+  smUnit(4).io.isAbrt := lvdsSMAbrt(2)
+  smUnit(6).io.isAbrt := lvdsSMAbrt(3)
+
   smUnit(1).io.deq := lvdsSMDeq(0)
   smUnit(3).io.deq := lvdsSMDeq(1)
   smUnit(5).io.deq := lvdsSMDeq(2)
@@ -153,6 +164,16 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{
   smUnit(5).io.enq := interface.io.uSMenq(2)
   smUnit(7).io.enq := interface.io.uSMenq(3)
 
+  smUnit(1).io.isComf := RegNext( smUnit(1).io.enq, false.B )
+  smUnit(3).io.isComf := RegNext( smUnit(3).io.enq, false.B )
+  smUnit(5).io.isComf := RegNext( smUnit(5).io.enq, false.B )
+  smUnit(7).io.isComf := RegNext( smUnit(7).io.enq, false.B )
+
+  smUnit(1).io.isAbrt := false.B
+  smUnit(3).io.isAbrt := false.B
+  smUnit(5).io.isAbrt := false.B
+  smUnit(7).io.isAbrt := false.B
+
   for( i <- 0 until 8 ){
     interface.io.smUsedDepth(i) := smUnit(i).io.cnt
     smUnit(i).io.flush := interface.io.isSMReset(i)
@@ -257,7 +278,6 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{
 
 }
 
-
 trait MstSlvSwitchMaster{ this: MstSlvSwitchBase =>
 
   when( interface.io.cReg.modeSel === true.B ){
@@ -269,16 +289,24 @@ trait MstSlvSwitchMaster{ this: MstSlvSwitchBase =>
 
     when( interface.io.txReq.bits.rxSM === 0.U ){
       smUnit(0).io.sram_w := masterParser.io.sram_w
-      lvdsSMEnq(0)    := masterParser.io.rxEnq
+      lvdsSMEnq(0)  := masterParser.io.rxEnq
+      lvdsSMComf(0) := RegNext(masterParser.io.rxEnq, false.B)
+      lvdsSMAbrt(0) := false.B
     } .elsewhen( interface.io.txReq.bits.rxSM === 1.U ){
       smUnit(2).io.sram_w := masterParser.io.sram_w
-      lvdsSMEnq(1)    := masterParser.io.rxEnq
+      lvdsSMEnq(1)  := masterParser.io.rxEnq
+      lvdsSMComf(1) := RegNext(masterParser.io.rxEnq, false.B)
+      lvdsSMAbrt(1) := false.B
     } .elsewhen( interface.io.txReq.bits.rxSM === 2.U ){
       smUnit(4).io.sram_w := masterParser.io.sram_w
-      lvdsSMEnq(2)    := masterParser.io.rxEnq
+      lvdsSMEnq(2)  := masterParser.io.rxEnq
+      lvdsSMComf(2) := RegNext(masterParser.io.rxEnq, false.B)
+      lvdsSMAbrt(2) := false.B
     } .elsewhen( interface.io.txReq.bits.rxSM === 3.U ){
       smUnit(6).io.sram_w := masterParser.io.sram_w
-      lvdsSMEnq(3)    := masterParser.io.rxEnq
+      lvdsSMEnq(3)  := masterParser.io.rxEnq
+      lvdsSMComf(3) := RegNext(masterParser.io.rxEnq, false.B)
+      lvdsSMAbrt(3) := false.B
     }
 
     when( interface.io.txReq.bits.txSM === 0.U ){
@@ -346,6 +374,16 @@ trait MstSlvSwitchSlave{ this: MstSlvSwitchBase =>
     lvdsSMEnq(2) := slaveParser.io.dSMenq(2)
     lvdsSMEnq(3) := slaveParser.io.dSMenq(3)
 
+    lvdsSMComf(0) := slaveParser.io.downRecStat.isFinish
+    lvdsSMComf(1) := slaveParser.io.downRecStat.isFinish
+    lvdsSMComf(2) := slaveParser.io.downRecStat.isFinish
+    lvdsSMComf(3) := slaveParser.io.downRecStat.isFinish
+
+    lvdsSMAbrt(0) := slaveParser.io.downRecStat.isRecError
+    lvdsSMAbrt(1) := slaveParser.io.downRecStat.isRecError
+    lvdsSMAbrt(2) := slaveParser.io.downRecStat.isRecError
+    lvdsSMAbrt(3) := slaveParser.io.downRecStat.isRecError
+
     lvdsSMDeq(0) := slaveParser.io.uSMdeq(0)
     lvdsSMDeq(1) := slaveParser.io.uSMdeq(1)
     lvdsSMDeq(2) := slaveParser.io.uSMdeq(2)

src/main/scala/backBoard/shin/SMUnit.scala

@@ -34,25 +34,29 @@ class SMUnitIO(depth: Int) extends Bundle {
   val cnt  = Output(UInt(8.W))
 
   val flush = Input(Bool())
-
+  val isComf = Input(Bool())
+  val isAbrt = Input(Bool())
 }
 
 abstract class SMUnitBase(depth: Int = 4) extends Module with RequireAsyncReset{
+  require(depth <= 4)
   val io: SMUnitIO = IO(new SMUnitIO(depth))
  
 
   val wPtr = RegInit(0.U((log2Ceil(depth)+1).W))
   val rPtr = RegInit(0.U((log2Ceil(depth)+1).W))
+  val cPtr = RegInit(0.U((log2Ceil(depth)+1).W))
 
   val isFull = (wPtr ^ rPtr) === (1.U << log2Ceil(depth))
-
-  val isEmpty = ( wPtr === rPtr )
+  val isEmpty = ( cPtr === rPtr )
 
   when(io.flush){
     wPtr := 0.U
   } .elsewhen( io.enq & ~isFull ){
     wPtr := wPtr + 1.U
     // assert( ~isFull)
+  } .elsewhen( io.isAbrt ){
+    wPtr := cPtr
   }
 
   when(io.flush){
@@ -82,24 +86,17 @@ abstract class SMUnitBase(depth: Int = 4) extends Module with RequireAsyncReset{
     }
   }
 
-
-
   io.sram_r.datar := Mux1H( ( 0 until depth).map{ i =>
     ( (rPtr(log2Ceil(depth)-1, 0)) === i.U ) -> io.sram(i).rd.datar
   })
 
-  val cnt = RegInit(0.U((log2Ceil(depth+1)).W)); io.cnt := cnt
+  io.cnt := cPtr - rPtr
 
-  when( io.flush ){
-    cnt := 0.U
-  } .elsewhen( io.enq & ~isFull ){
-    cnt := cnt + 1.U
-    assert(cnt =/= depth.U)
-  } .elsewhen( io.deq & ~isEmpty ){
-    cnt := cnt - 1.U
-    assert(cnt =/= 0.U)
+  when( io.isComf ){
+    cPtr := wPtr
   }
 
+
 }
 
 class SMUnit(depth: Int = 4) extends SMUnitBase(depth) {