From 6cf1e217746b26748eb1e439fef9c0c054785ba6 Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Wed, 3 Sep 2025 18:04:10 +0800 Subject: [PATCH] =?UTF-8?q?SM=E9=99=A4=E9=94=99=E4=BD=BF=E7=94=A8commit?= =?UTF-8?q?=E6=8C=87=E9=92=88=E7=AD=96=E7=95=A5=EF=BC=8C=E9=9C=80=E8=A6=81?= =?UTF-8?q?=E6=B5=8B=E8=AF=95=E8=A6=86=E7=9B=961=EF=BC=89=E4=B8=80?= =?UTF-8?q?=E4=B8=AA=E5=8C=85=E4=B8=AD=E5=90=8C=E6=97=B6=E5=86=99=E5=85=A5?= =?UTF-8?q?=E6=93=8D=E4=BD=9C0~4=E4=B8=AAsm=E7=9A=841~4=E4=B8=AA=E5=85=83?= =?UTF-8?q?=E7=B4=A0=E5=90=8E=E5=87=BA=E9=94=99=EF=BC=8C=E6=98=AF=E5=90=A6?= =?UTF-8?q?=E5=AF=B9=E5=90=8E=E7=BB=ADSM=E6=93=8D=E4=BD=9C=E5=8F=91?= =?UTF-8?q?=E7=94=9F=E5=BD=B1=E5=93=8D=EF=BC=8C2=EF=BC=89=E5=B0=9D?= =?UTF-8?q?=E8=AF=95=E5=9C=A8SM=E7=A9=BA=E6=97=B6=E8=AF=BB=EF=BC=8C?= =?UTF-8?q?=E5=B0=9D=E8=AF=95=E5=9C=A8SM=E6=BB=A1=E6=97=B6=E5=86=99?= =?UTF-8?q?=EF=BC=8C=E6=98=AF=E5=90=A6=E4=BC=9A=E5=AF=B9=E5=90=8E=E7=BB=AD?= =?UTF-8?q?=E6=8F=90=E4=BA=A4=E6=93=8D=E4=BD=9C=E4=BA=A7=E7=94=9F=E5=BD=B1?= =?UTF-8?q?=E5=93=8D=203=EF=BC=89=E5=AF=84=E5=AD=98=E5=99=A80x538=E8=AE=B0?= =?UTF-8?q?=E5=BD=95=E7=9A=84=E6=97=B6=E9=97=B4=E4=B8=8D=E4=BC=9A=E5=8C=BA?= =?UTF-8?q?=E5=88=86=E6=98=AF=E5=90=A6=E6=98=AF=E9=94=99=E8=AF=AF=E5=8C=85?= =?UTF-8?q?4=EF=BC=89=E5=9C=A8=E5=89=8D=E8=BF=B0=E5=A4=9A=E6=AC=A1?= =?UTF-8?q?=E5=A4=8D=E6=9D=82=E6=93=8D=E4=BD=9C=E5=90=8E=E5=AF=84=E5=AD=98?= =?UTF-8?q?=E5=99=A80x301=E7=9A=84=E8=AE=A1=E6=95=B0=E6=98=AF=E5=90=A6?= =?UTF-8?q?=E6=AD=A3=E5=B8=B8=205=EF=BC=89=E4=BB=8Espi=E4=BE=A7=E5=86=99?= =?UTF-8?q?=E5=85=A5=E6=98=AF=E5=90=A6=E6=AD=A3=E5=B8=B8=206=EF=BC=89?= =?UTF-8?q?=E4=B8=BB=E7=AB=99=E5=86=99=E5=85=A5=E7=9A=84=E5=8C=85=E9=94=99?= =?UTF-8?q?=E8=AF=AF=E5=B0=86=E4=B8=8D=E4=BC=9A=E5=88=A4=E6=96=AD?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../scala/backBoard/shin/MstSlvSwitch.scala | 50 ++++++++++++++++--- src/main/scala/backBoard/shin/SMUnit.scala | 25 ++++------ 2 files changed, 55 insertions(+), 20 deletions(-) diff --git a/src/main/scala/backBoard/shin/MstSlvSwitch.scala b/src/main/scala/backBoard/shin/MstSlvSwitch.scala index 688c892..e478fea 100644 --- a/src/main/scala/backBoard/shin/MstSlvSwitch.scala +++ b/src/main/scala/backBoard/shin/MstSlvSwitch.scala @@ -120,13 +120,24 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{ val lvdsSMEnq = for( i <- 0 until 4 ) yield WireDefault(false.B); interface.io.lvdsSMEnq := lvdsSMEnq val lvdsSMDeq = for( i <- 0 until 4 ) yield WireDefault(false.B); interface.io.lvdsSMDeq := lvdsSMDeq - + val lvdsSMComf = for( i <- 0 until 4 ) yield WireDefault(false.B) + val lvdsSMAbrt = for( i <- 0 until 4 ) yield WireDefault(false.B) smUnit(0).io.enq := lvdsSMEnq(0) smUnit(2).io.enq := lvdsSMEnq(1) smUnit(4).io.enq := lvdsSMEnq(2) smUnit(6).io.enq := lvdsSMEnq(3) + smUnit(0).io.isComf := lvdsSMComf(0) + smUnit(2).io.isComf := lvdsSMComf(1) + smUnit(4).io.isComf := lvdsSMComf(2) + smUnit(6).io.isComf := lvdsSMComf(3) + + smUnit(0).io.isAbrt := lvdsSMAbrt(0) + smUnit(2).io.isAbrt := lvdsSMAbrt(1) + smUnit(4).io.isAbrt := lvdsSMAbrt(2) + smUnit(6).io.isAbrt := lvdsSMAbrt(3) + smUnit(1).io.deq := lvdsSMDeq(0) smUnit(3).io.deq := lvdsSMDeq(1) smUnit(5).io.deq := lvdsSMDeq(2) @@ -153,6 +164,16 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{ smUnit(5).io.enq := interface.io.uSMenq(2) smUnit(7).io.enq := interface.io.uSMenq(3) + smUnit(1).io.isComf := RegNext( smUnit(1).io.enq, false.B ) + smUnit(3).io.isComf := RegNext( smUnit(3).io.enq, false.B ) + smUnit(5).io.isComf := RegNext( smUnit(5).io.enq, false.B ) + smUnit(7).io.isComf := RegNext( smUnit(7).io.enq, false.B ) + + smUnit(1).io.isAbrt := false.B + smUnit(3).io.isAbrt := false.B + smUnit(5).io.isAbrt := false.B + smUnit(7).io.isAbrt := false.B + for( i <- 0 until 8 ){ interface.io.smUsedDepth(i) := smUnit(i).io.cnt smUnit(i).io.flush := interface.io.isSMReset(i) @@ -257,7 +278,6 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{ } - trait MstSlvSwitchMaster{ this: MstSlvSwitchBase => when( interface.io.cReg.modeSel === true.B ){ @@ -269,16 +289,24 @@ trait MstSlvSwitchMaster{ this: MstSlvSwitchBase => when( interface.io.txReq.bits.rxSM === 0.U ){ smUnit(0).io.sram_w := masterParser.io.sram_w - lvdsSMEnq(0) := masterParser.io.rxEnq + lvdsSMEnq(0) := masterParser.io.rxEnq + lvdsSMComf(0) := RegNext(masterParser.io.rxEnq, false.B) + lvdsSMAbrt(0) := false.B } .elsewhen( interface.io.txReq.bits.rxSM === 1.U ){ smUnit(2).io.sram_w := masterParser.io.sram_w - lvdsSMEnq(1) := masterParser.io.rxEnq + lvdsSMEnq(1) := masterParser.io.rxEnq + lvdsSMComf(1) := RegNext(masterParser.io.rxEnq, false.B) + lvdsSMAbrt(1) := false.B } .elsewhen( interface.io.txReq.bits.rxSM === 2.U ){ smUnit(4).io.sram_w := masterParser.io.sram_w - lvdsSMEnq(2) := masterParser.io.rxEnq + lvdsSMEnq(2) := masterParser.io.rxEnq + lvdsSMComf(2) := RegNext(masterParser.io.rxEnq, false.B) + lvdsSMAbrt(2) := false.B } .elsewhen( interface.io.txReq.bits.rxSM === 3.U ){ smUnit(6).io.sram_w := masterParser.io.sram_w - lvdsSMEnq(3) := masterParser.io.rxEnq + lvdsSMEnq(3) := masterParser.io.rxEnq + lvdsSMComf(3) := RegNext(masterParser.io.rxEnq, false.B) + lvdsSMAbrt(3) := false.B } when( interface.io.txReq.bits.txSM === 0.U ){ @@ -346,6 +374,16 @@ trait MstSlvSwitchSlave{ this: MstSlvSwitchBase => lvdsSMEnq(2) := slaveParser.io.dSMenq(2) lvdsSMEnq(3) := slaveParser.io.dSMenq(3) + lvdsSMComf(0) := slaveParser.io.downRecStat.isFinish + lvdsSMComf(1) := slaveParser.io.downRecStat.isFinish + lvdsSMComf(2) := slaveParser.io.downRecStat.isFinish + lvdsSMComf(3) := slaveParser.io.downRecStat.isFinish + + lvdsSMAbrt(0) := slaveParser.io.downRecStat.isRecError + lvdsSMAbrt(1) := slaveParser.io.downRecStat.isRecError + lvdsSMAbrt(2) := slaveParser.io.downRecStat.isRecError + lvdsSMAbrt(3) := slaveParser.io.downRecStat.isRecError + lvdsSMDeq(0) := slaveParser.io.uSMdeq(0) lvdsSMDeq(1) := slaveParser.io.uSMdeq(1) lvdsSMDeq(2) := slaveParser.io.uSMdeq(2) diff --git a/src/main/scala/backBoard/shin/SMUnit.scala b/src/main/scala/backBoard/shin/SMUnit.scala index 15acb50..3ffeb7c 100644 --- a/src/main/scala/backBoard/shin/SMUnit.scala +++ b/src/main/scala/backBoard/shin/SMUnit.scala @@ -34,25 +34,29 @@ class SMUnitIO(depth: Int) extends Bundle { val cnt = Output(UInt(8.W)) val flush = Input(Bool()) - + val isComf = Input(Bool()) + val isAbrt = Input(Bool()) } abstract class SMUnitBase(depth: Int = 4) extends Module with RequireAsyncReset{ + require(depth <= 4) val io: SMUnitIO = IO(new SMUnitIO(depth)) val wPtr = RegInit(0.U((log2Ceil(depth)+1).W)) val rPtr = RegInit(0.U((log2Ceil(depth)+1).W)) + val cPtr = RegInit(0.U((log2Ceil(depth)+1).W)) val isFull = (wPtr ^ rPtr) === (1.U << log2Ceil(depth)) - - val isEmpty = ( wPtr === rPtr ) + val isEmpty = ( cPtr === rPtr ) when(io.flush){ wPtr := 0.U } .elsewhen( io.enq & ~isFull ){ wPtr := wPtr + 1.U // assert( ~isFull) + } .elsewhen( io.isAbrt ){ + wPtr := cPtr } when(io.flush){ @@ -82,24 +86,17 @@ abstract class SMUnitBase(depth: Int = 4) extends Module with RequireAsyncReset{ } } - - io.sram_r.datar := Mux1H( ( 0 until depth).map{ i => ( (rPtr(log2Ceil(depth)-1, 0)) === i.U ) -> io.sram(i).rd.datar }) - val cnt = RegInit(0.U((log2Ceil(depth+1)).W)); io.cnt := cnt + io.cnt := cPtr - rPtr - when( io.flush ){ - cnt := 0.U - } .elsewhen( io.enq & ~isFull ){ - cnt := cnt + 1.U - assert(cnt =/= depth.U) - } .elsewhen( io.deq & ~isEmpty ){ - cnt := cnt - 1.U - assert(cnt =/= 0.U) + when( io.isComf ){ + cPtr := wPtr } + } class SMUnit(depth: Int = 4) extends SMUnitBase(depth) {