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CDRIn采样率改为8x，允许参数化

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This commit is contained in:
Ruige Lee
2025-04-02 15:44:32 +08:00
parent eec4d5c18a
commit 6c6cce1222
3 changed files with 42 additions and 33 deletions
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53
src/main/scala/backBoard/ebus/CDRIn.scala
View File

@@ -13,8 +13,7 @@ class CDRInIO extends Bundle{
abstract class CDRInBase extends Module{
def sampleRate: Int = 4
require( sampleRate == 4 )
def sampleRate: Int = 8
val io: CDRInIO = IO(new CDRInIO)
@@ -45,34 +44,44 @@ trait CDRInOverSample{ this: CDRInBase =>
// val syncSerDat =
// Mux1H( (0 until sampleRate).map{ i => (( arbSel === i.U ) -> ShiftRegister( sampleReg(i), 2) ) } )
val arbCnt = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegInit("b0001".U(sampleRate.W)) }
arbCnt := Cat( arbCnt(2,0), arbCnt.extract(3) )
val arbCnt = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegInit("b00000001".U(sampleRate.W)) }
arbCnt := Cat( arbCnt(sampleRate-2,0), arbCnt.extract(sampleRate-1) )
val arbLock = withClockAndReset(io.overCLK.asClock, reset.asBool){ Reg(UInt( sampleRate.W )) }
when( sampleReg(0) ^ sampleReg(1) ){
arbLock := arbCnt
}
val asyncSerDat = Mux1H(Seq(
(arbLock === "b0001".U & arbCnt === "b0001".U) -> sampleReg(3),
(arbLock === "b0001".U & arbCnt === "b0010".U) -> sampleReg(0),
(arbLock === "b0001".U & arbCnt === "b0100".U) -> sampleReg(1),
(arbLock === "b0001".U & arbCnt === "b1000".U) -> sampleReg(2),
val asyncSerDat = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegNext(
Mux1H(
// Seq(
// //(arbLock === "b0001".U & arbCnt === "b0001".U) -> sampleReg(3),
// (arbLock === (1.U << 0) & arbCnt === (1.U << 0)) -> sampleReg(3),
// (arbLock === (1.U << 0) & arbCnt === (1.U << 1)) -> sampleReg(0),
// (arbLock === (1.U << 0) & arbCnt === (1.U << 2)) -> sampleReg(1),
// (arbLock === (1.U << 0) & arbCnt === (1.U << 3)) -> sampleReg(2),
(arbLock === "b0010".U & arbCnt === "b0001".U) -> sampleReg(2),
(arbLock === "b0010".U & arbCnt === "b0010".U) -> sampleReg(3),
(arbLock === "b0010".U & arbCnt === "b0100".U) -> sampleReg(0),
(arbLock === "b0010".U & arbCnt === "b1000".U) -> sampleReg(1),
// (arbLock === (1.U << 1) & arbCnt === (1.U << 0)) -> sampleReg(2),
// (arbLock === (1.U << 1) & arbCnt === (1.U << 1)) -> sampleReg(3),
// (arbLock === (1.U << 1) & arbCnt === (1.U << 2)) -> sampleReg(0),
// (arbLock === (1.U << 1) & arbCnt === (1.U << 3)) -> sampleReg(1),
(arbLock === "b0100".U & arbCnt === "b0001".U) -> sampleReg(1),
(arbLock === "b0100".U & arbCnt === "b0010".U) -> sampleReg(2),
(arbLock === "b0100".U & arbCnt === "b0100".U) -> sampleReg(3),
(arbLock === "b0100".U & arbCnt === "b1000".U) -> sampleReg(0),
// (arbLock === (1.U << 2) & arbCnt === (1.U << 0)) -> sampleReg(1),
// (arbLock === (1.U << 2) & arbCnt === (1.U << 1)) -> sampleReg(2),
// (arbLock === (1.U << 2) & arbCnt === (1.U << 2)) -> sampleReg(3),
// (arbLock === (1.U << 2) & arbCnt === (1.U << 3)) -> sampleReg(0),
(arbLock === "b1000".U & arbCnt === "b0001".U) -> sampleReg(0),
(arbLock === "b1000".U & arbCnt === "b0010".U) -> sampleReg(1),
(arbLock === "b1000".U & arbCnt === "b0100".U) -> sampleReg(2),
(arbLock === "b1000".U & arbCnt === "b1000".U) -> sampleReg(3),
))
// (arbLock === (1.U << 3) & arbCnt === (1.U << 0)) -> sampleReg(0),
// (arbLock === (1.U << 3) & arbCnt === (1.U << 1)) -> sampleReg(1),
// (arbLock === (1.U << 3) & arbCnt === (1.U << 2)) -> sampleReg(2),
// (arbLock === (1.U << 3) & arbCnt === (1.U << 3)) -> sampleReg(3),
// )
(for { i <- 0 until sampleRate; j <- 0 until sampleRate } yield {
//跳变沿到来锁定的位置 锁定拍当前所在的位置 选择锁定拍后一拍的值认为是正确值
((arbLock === (1.U << i)) & (arbCnt === (1.U << j))) -> sampleReg((sampleRate - 1 - i + j) % sampleRate)
})
)
)}
val syncSerDat = ShiftRegister( asyncSerDat, 2 )

10
tb/verilator/SimTop.v
View File

@@ -13,7 +13,7 @@ module SimTop (
input clock, //100MHz
input reset,
input clk400,
input clk800,
output [7:0] gpio_o,
input [7:0] gpio_i
@@ -205,7 +205,7 @@ ExampleRocketSystem s_rocket_mst(
.interrupts(2'b0),
.cdrInIO_overCLK(clk400),
.cdrInIO_overCLK(clk800),
.cdrInIO_dDatIn(1'b0),
.cdrInIO_uDatIn(uDatSer[0]),
.cdrInIO_isLast(1'b0),
@@ -398,7 +398,7 @@ ExampleRocketSystem s_rocket_slv0(
.interrupts(2'b0),
.cdrInIO_overCLK(clk400),
.cdrInIO_overCLK(clk800),
.cdrInIO_dDatIn(dDatSer[0]),
.cdrInIO_uDatIn(uDatSer[1]),
.cdrInIO_isLast(1'b0),
@@ -591,7 +591,7 @@ ExampleRocketSystem s_rocket_slv1(
.interrupts(2'b0),
.cdrInIO_overCLK(clk400),
.cdrInIO_overCLK(clk800),
.cdrInIO_dDatIn(dDatSer[1]),
.cdrInIO_uDatIn(uDatSer[2]),
.cdrInIO_isLast(1'b0),
@@ -784,7 +784,7 @@ ExampleRocketSystem s_rocket_slv2(
.interrupts(2'b0),
.cdrInIO_overCLK(clk400),
.cdrInIO_overCLK(clk800),
.cdrInIO_dDatIn(dDatSer[2]),
.cdrInIO_uDatIn(),
.cdrInIO_isLast(1'b1),

12
tb/verilator/sim_main.cpp
View File

@@ -125,7 +125,7 @@ int main(int argc, char **argv, char **env) {
top->reset = 1;
top->clock = 0;
top->clk400 = 0;
top->clk800 = 0;
while(!Verilated::gotFinish()) {
@@ -172,11 +172,11 @@ static void init_and_clock(){
main_cycle ++;
}
uint8_t phase = 4;
if ( main_time % 10 == (0+phase) ) {
top->clk400 = 1;
} else if ( main_time % 10 == (5+phase) ) {
top->clk400 = 0;
uint8_t phase = 1;
if ( main_time % 5 == (0+phase) ) {
top->clk800 = 1;
} else if ( main_time % 5 == (2+phase) ) {
top->clk800 = 0;
}