From 6c6cce12229199e99c5192c13da221b2516fa593 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Wed, 2 Apr 2025 15:44:32 +0800 Subject: [PATCH] =?UTF-8?q?CDRIn=E9=87=87=E6=A0=B7=E7=8E=87=E6=94=B9?= =?UTF-8?q?=E4=B8=BA8x=EF=BC=8C=E5=85=81=E8=AE=B8=E5=8F=82=E6=95=B0?= =?UTF-8?q?=E5=8C=96?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/ebus/CDRIn.scala | 53 +++++++++++++---------- tb/verilator/SimTop.v | 10 ++--- tb/verilator/sim_main.cpp | 12 ++--- 3 files changed, 42 insertions(+), 33 deletions(-) diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala index 0ba1922..5370467 100644 --- a/src/main/scala/backBoard/ebus/CDRIn.scala +++ b/src/main/scala/backBoard/ebus/CDRIn.scala @@ -13,8 +13,7 @@ class CDRInIO extends Bundle{ abstract class CDRInBase extends Module{ - def sampleRate: Int = 4 - require( sampleRate == 4 ) + def sampleRate: Int = 8 val io: CDRInIO = IO(new CDRInIO) @@ -45,34 +44,44 @@ trait CDRInOverSample{ this: CDRInBase => // val syncSerDat = // Mux1H( (0 until sampleRate).map{ i => (( arbSel === i.U ) -> ShiftRegister( sampleReg(i), 2) ) } ) - val arbCnt = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegInit("b0001".U(sampleRate.W)) } - arbCnt := Cat( arbCnt(2,0), arbCnt.extract(3) ) + val arbCnt = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegInit("b00000001".U(sampleRate.W)) } + arbCnt := Cat( arbCnt(sampleRate-2,0), arbCnt.extract(sampleRate-1) ) val arbLock = withClockAndReset(io.overCLK.asClock, reset.asBool){ Reg(UInt( sampleRate.W )) } when( sampleReg(0) ^ sampleReg(1) ){ arbLock := arbCnt } - val asyncSerDat = Mux1H(Seq( - (arbLock === "b0001".U & arbCnt === "b0001".U) -> sampleReg(3), - (arbLock === "b0001".U & arbCnt === "b0010".U) -> sampleReg(0), - (arbLock === "b0001".U & arbCnt === "b0100".U) -> sampleReg(1), - (arbLock === "b0001".U & arbCnt === "b1000".U) -> sampleReg(2), + val asyncSerDat = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegNext( + Mux1H( + // Seq( + // //(arbLock === "b0001".U & arbCnt === "b0001".U) -> sampleReg(3), + // (arbLock === (1.U << 0) & arbCnt === (1.U << 0)) -> sampleReg(3), + // (arbLock === (1.U << 0) & arbCnt === (1.U << 1)) -> sampleReg(0), + // (arbLock === (1.U << 0) & arbCnt === (1.U << 2)) -> sampleReg(1), + // (arbLock === (1.U << 0) & arbCnt === (1.U << 3)) -> sampleReg(2), - (arbLock === "b0010".U & arbCnt === "b0001".U) -> sampleReg(2), - (arbLock === "b0010".U & arbCnt === "b0010".U) -> sampleReg(3), - (arbLock === "b0010".U & arbCnt === "b0100".U) -> sampleReg(0), - (arbLock === "b0010".U & arbCnt === "b1000".U) -> sampleReg(1), + // (arbLock === (1.U << 1) & arbCnt === (1.U << 0)) -> sampleReg(2), + // (arbLock === (1.U << 1) & arbCnt === (1.U << 1)) -> sampleReg(3), + // (arbLock === (1.U << 1) & arbCnt === (1.U << 2)) -> sampleReg(0), + // (arbLock === (1.U << 1) & arbCnt === (1.U << 3)) -> sampleReg(1), - (arbLock === "b0100".U & arbCnt === "b0001".U) -> sampleReg(1), - (arbLock === "b0100".U & arbCnt === "b0010".U) -> sampleReg(2), - (arbLock === "b0100".U & arbCnt === "b0100".U) -> sampleReg(3), - (arbLock === "b0100".U & arbCnt === "b1000".U) -> sampleReg(0), + // (arbLock === (1.U << 2) & arbCnt === (1.U << 0)) -> sampleReg(1), + // (arbLock === (1.U << 2) & arbCnt === (1.U << 1)) -> sampleReg(2), + // (arbLock === (1.U << 2) & arbCnt === (1.U << 2)) -> sampleReg(3), + // (arbLock === (1.U << 2) & arbCnt === (1.U << 3)) -> sampleReg(0), - (arbLock === "b1000".U & arbCnt === "b0001".U) -> sampleReg(0), - (arbLock === "b1000".U & arbCnt === "b0010".U) -> sampleReg(1), - (arbLock === "b1000".U & arbCnt === "b0100".U) -> sampleReg(2), - (arbLock === "b1000".U & arbCnt === "b1000".U) -> sampleReg(3), - )) + // (arbLock === (1.U << 3) & arbCnt === (1.U << 0)) -> sampleReg(0), + // (arbLock === (1.U << 3) & arbCnt === (1.U << 1)) -> sampleReg(1), + // (arbLock === (1.U << 3) & arbCnt === (1.U << 2)) -> sampleReg(2), + // (arbLock === (1.U << 3) & arbCnt === (1.U << 3)) -> sampleReg(3), + // ) + + (for { i <- 0 until sampleRate; j <- 0 until sampleRate } yield { + //跳变沿到来锁定的位置 锁定拍当前所在的位置 选择锁定拍后一拍的值认为是正确值 + ((arbLock === (1.U << i)) & (arbCnt === (1.U << j))) -> sampleReg((sampleRate - 1 - i + j) % sampleRate) + }) + ) + )} val syncSerDat = ShiftRegister( asyncSerDat, 2 ) diff --git a/tb/verilator/SimTop.v b/tb/verilator/SimTop.v index a6c1892..7127dea 100644 --- a/tb/verilator/SimTop.v +++ b/tb/verilator/SimTop.v @@ -13,7 +13,7 @@ module SimTop ( input clock, //100MHz input reset, - input clk400, + input clk800, output [7:0] gpio_o, input [7:0] gpio_i @@ -205,7 +205,7 @@ ExampleRocketSystem s_rocket_mst( .interrupts(2'b0), - .cdrInIO_overCLK(clk400), + .cdrInIO_overCLK(clk800), .cdrInIO_dDatIn(1'b0), .cdrInIO_uDatIn(uDatSer[0]), .cdrInIO_isLast(1'b0), @@ -398,7 +398,7 @@ ExampleRocketSystem s_rocket_slv0( .interrupts(2'b0), - .cdrInIO_overCLK(clk400), + .cdrInIO_overCLK(clk800), .cdrInIO_dDatIn(dDatSer[0]), .cdrInIO_uDatIn(uDatSer[1]), .cdrInIO_isLast(1'b0), @@ -591,7 +591,7 @@ ExampleRocketSystem s_rocket_slv1( .interrupts(2'b0), - .cdrInIO_overCLK(clk400), + .cdrInIO_overCLK(clk800), .cdrInIO_dDatIn(dDatSer[1]), .cdrInIO_uDatIn(uDatSer[2]), .cdrInIO_isLast(1'b0), @@ -784,7 +784,7 @@ ExampleRocketSystem s_rocket_slv2( .interrupts(2'b0), - .cdrInIO_overCLK(clk400), + .cdrInIO_overCLK(clk800), .cdrInIO_dDatIn(dDatSer[2]), .cdrInIO_uDatIn(), .cdrInIO_isLast(1'b1), diff --git a/tb/verilator/sim_main.cpp b/tb/verilator/sim_main.cpp index 4af8d9f..0857b9d 100644 --- a/tb/verilator/sim_main.cpp +++ b/tb/verilator/sim_main.cpp @@ -125,7 +125,7 @@ int main(int argc, char **argv, char **env) { top->reset = 1; top->clock = 0; - top->clk400 = 0; + top->clk800 = 0; while(!Verilated::gotFinish()) { @@ -172,11 +172,11 @@ static void init_and_clock(){ main_cycle ++; } - uint8_t phase = 4; - if ( main_time % 10 == (0+phase) ) { - top->clk400 = 1; - } else if ( main_time % 10 == (5+phase) ) { - top->clk400 = 0; + uint8_t phase = 1; + if ( main_time % 5 == (0+phase) ) { + top->clk800 = 1; + } else if ( main_time % 5 == (2+phase) ) { + top->clk800 = 0; }