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CDRIn采样率改为8x，允许参数化

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This commit is contained in:
Ruige Lee
2025-04-02 15:44:32 +08:00
parent eec4d5c18a
commit 6c6cce1222
3 changed files with 42 additions and 33 deletions
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12
tb/verilator/sim_main.cpp
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@@ -125,7 +125,7 @@ int main(int argc, char **argv, char **env) {
top->reset = 1;
top->clock = 0;
top->clk400 = 0;
top->clk800 = 0;
while(!Verilated::gotFinish()) {
@@ -172,11 +172,11 @@ static void init_and_clock(){
main_cycle ++;
}
uint8_t phase = 4;
if ( main_time % 10 == (0+phase) ) {
top->clk400 = 1;
} else if ( main_time % 10 == (5+phase) ) {
top->clk400 = 0;
uint8_t phase = 1;
if ( main_time % 5 == (0+phase) ) {
top->clk800 = 1;
} else if ( main_time % 5 == (2+phase) ) {
top->clk800 = 0;
}