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CDRIn采样率改为8x，允许参数化

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This commit is contained in:
Ruige Lee
2025-04-02 15:44:32 +08:00
parent eec4d5c18a
commit 6c6cce1222
3 changed files with 42 additions and 33 deletions
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10
tb/verilator/SimTop.v
View File

@@ -13,7 +13,7 @@ module SimTop (
input clock, //100MHz
input reset,
input clk400,
input clk800,
output [7:0] gpio_o,
input [7:0] gpio_i
@@ -205,7 +205,7 @@ ExampleRocketSystem s_rocket_mst(
.interrupts(2'b0),
.cdrInIO_overCLK(clk400),
.cdrInIO_overCLK(clk800),
.cdrInIO_dDatIn(1'b0),
.cdrInIO_uDatIn(uDatSer[0]),
.cdrInIO_isLast(1'b0),
@@ -398,7 +398,7 @@ ExampleRocketSystem s_rocket_slv0(
.interrupts(2'b0),
.cdrInIO_overCLK(clk400),
.cdrInIO_overCLK(clk800),
.cdrInIO_dDatIn(dDatSer[0]),
.cdrInIO_uDatIn(uDatSer[1]),
.cdrInIO_isLast(1'b0),
@@ -591,7 +591,7 @@ ExampleRocketSystem s_rocket_slv1(
.interrupts(2'b0),
.cdrInIO_overCLK(clk400),
.cdrInIO_overCLK(clk800),
.cdrInIO_dDatIn(dDatSer[1]),
.cdrInIO_uDatIn(uDatSer[2]),
.cdrInIO_isLast(1'b0),
@@ -784,7 +784,7 @@ ExampleRocketSystem s_rocket_slv2(
.interrupts(2'b0),
.cdrInIO_overCLK(clk400),
.cdrInIO_overCLK(clk800),
.cdrInIO_dDatIn(dDatSer[2]),
.cdrInIO_uDatIn(),
.cdrInIO_isLast(1'b1),

12
tb/verilator/sim_main.cpp
View File

@@ -125,7 +125,7 @@ int main(int argc, char **argv, char **env) {
top->reset = 1;
top->clock = 0;
top->clk400 = 0;
top->clk800 = 0;
while(!Verilated::gotFinish()) {
@@ -172,11 +172,11 @@ static void init_and_clock(){
main_cycle ++;
}
uint8_t phase = 4;
if ( main_time % 10 == (0+phase) ) {
top->clk400 = 1;
} else if ( main_time % 10 == (5+phase) ) {
top->clk400 = 0;
uint8_t phase = 1;
if ( main_time % 5 == (0+phase) ) {
top->clk800 = 1;
} else if ( main_time % 5 == (2+phase) ) {
top->clk800 = 0;
}