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仅当sm为空时方可修改sm的触发长度，注意cnt=cPtr-rPtr，之前可能wPtr已经移动（可能撤销）

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RuigeLee
2025-09-11 11:01:50 +08:00
parent 139035e79e
commit 68f3c2ac89
1 changed files with 14 additions and 9 deletions
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23
src/main/scala/backBoard/shin/Interface.scala
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@@ -687,17 +687,22 @@ trait InterfaceCheckSM{ this: InterfaceBase =>
cReg.smUsedDepth(i) := io.smUsedDepth(i) cReg.smUsedDepth(i) := io.smUsedDepth(i)
cReg.smTrigLen(i) := Cat( smTrigLen_H(i), smTrigLen_L(i) ) cReg.smTrigLen(i) := Cat( smTrigLen_H(i), smTrigLen_L(i) )
when( isEnW & addrw === ("h303".U(16.W) + (i*4).U) ){ when( cReg.smUsedDepth(i) === 0.U ){
smTrigLen_H(i) := dataw when( isEnW & addrw === ("h303".U(16.W) + (i*4).U) ){
} .elsewhen( io.lvds.isEnW & io.lvds.addrw === ("h303".U(16.W) + (i*4).U)){ smTrigLen_H(i) := dataw
smTrigLen_H(i) := io.lvds.dataw } .elsewhen( io.lvds.isEnW & io.lvds.addrw === ("h303".U(16.W) + (i*4).U)){
smTrigLen_H(i) := io.lvds.dataw
}
when( isEnW & addrw === ("h302".U(16.W) + (i*4).U) ){
smTrigLen_L(i) := dataw
} .elsewhen( io.lvds.isEnW & io.lvds.addrw === ("h302".U(16.W) + (i*4).U)){
smTrigLen_L(i) := io.lvds.dataw
}
} }
when( isEnW & addrw === ("h302".U(16.W) + (i*4).U) ){
smTrigLen_L(i) := dataw
} .elsewhen( io.lvds.isEnW & io.lvds.addrw === ("h302".U(16.W) + (i*4).U)){
smTrigLen_L(i) := io.lvds.dataw
}
} }