diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index d0a8faf..51e3e26 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -687,17 +687,22 @@ trait InterfaceCheckSM{ this: InterfaceBase =>
     cReg.smUsedDepth(i) := io.smUsedDepth(i)
     cReg.smTrigLen(i) := Cat( smTrigLen_H(i), smTrigLen_L(i) )
 
-    when( isEnW & addrw === ("h303".U(16.W) + (i*4).U) ){
-      smTrigLen_H(i) := dataw
-    } .elsewhen( io.lvds.isEnW & io.lvds.addrw === ("h303".U(16.W) + (i*4).U)){
-      smTrigLen_H(i) := io.lvds.dataw
+    when( cReg.smUsedDepth(i) === 0.U ){
+      when( isEnW & addrw === ("h303".U(16.W) + (i*4).U) ){
+        smTrigLen_H(i) := dataw
+      } .elsewhen( io.lvds.isEnW & io.lvds.addrw === ("h303".U(16.W) + (i*4).U)){
+        smTrigLen_H(i) := io.lvds.dataw
+      }
+
+      when( isEnW & addrw === ("h302".U(16.W) + (i*4).U) ){
+        smTrigLen_L(i) := dataw
+      } .elsewhen( io.lvds.isEnW & io.lvds.addrw === ("h302".U(16.W) + (i*4).U)){
+        smTrigLen_L(i) := io.lvds.dataw
+      }
     }
 
-    when( isEnW & addrw === ("h302".U(16.W) + (i*4).U) ){
-      smTrigLen_L(i) := dataw
-    } .elsewhen( io.lvds.isEnW & io.lvds.addrw === ("h302".U(16.W) + (i*4).U)){
-      smTrigLen_L(i) := io.lvds.dataw
-    }
+
+
 
   }