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1、负负得正，spi方向让额外多读的一拍作为sm读取切换的延迟

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2、修复错误的sm读切换地址mask
This commit is contained in:
Ruige Lee
2025-05-22 19:43:49 +08:00
parent 0e3178c9da
commit 688a8cc1bd
1 changed files with 4 additions and 4 deletions
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8
src/main/scala/backBoard/shin/Interface.scala
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@@ -591,10 +591,10 @@ trait InterfaceCheckSM{ this: InterfaceBase =>
io.sram_w(2).enw := isEnW & (( addrw & "hF800".U ) === "h3000".U) io.sram_w(2).enw := isEnW & (( addrw & "hF800".U ) === "h3000".U)
io.sram_w(3).enw := isEnW & (( addrw & "hF800".U ) === "h4000".U) io.sram_w(3).enw := isEnW & (( addrw & "hF800".U ) === "h4000".U)
io.dSMdeq(0) := isEnR & (( addrr & "hF800".U ) === "h0800".U) & (addrr(10,0) === cReg.smTrigLen(0) - 1.U) io.dSMdeq(0) := isEnR & (( addrr & "hF800".U ) === "h0800".U) & (addrr(10,0) === cReg.smTrigLen(0) - 1.U + 1.U)
io.dSMdeq(1) := isEnR & (( addrr & "hF800".U ) === "h0800".U) & (addrr(10,0) === cReg.smTrigLen(2) - 1.U) io.dSMdeq(1) := isEnR & (( addrr & "hF800".U ) === "h1800".U) & (addrr(10,0) === cReg.smTrigLen(2) - 1.U + 1.U)
io.dSMdeq(2) := isEnR & (( addrr & "hF800".U ) === "h0800".U) & (addrr(10,0) === cReg.smTrigLen(4) - 1.U) io.dSMdeq(2) := isEnR & (( addrr & "hF800".U ) === "h2800".U) & (addrr(10,0) === cReg.smTrigLen(4) - 1.U + 1.U)
io.dSMdeq(3) := isEnR & (( addrr & "hF800".U ) === "h0800".U) & (addrr(10,0) === cReg.smTrigLen(6) - 1.U) io.dSMdeq(3) := isEnR & (( addrr & "hF800".U ) === "h3800".U) & (addrr(10,0) === cReg.smTrigLen(6) - 1.U + 1.U)
io.uSMenq(0) := isEnW & (( addrw & "hF800".U ) === "h1000".U) & (addrw(10,0) === cReg.smTrigLen(1) - 1.U) io.uSMenq(0) := isEnW & (( addrw & "hF800".U ) === "h1000".U) & (addrw(10,0) === cReg.smTrigLen(1) - 1.U)
io.uSMenq(1) := isEnW & (( addrw & "hF800".U ) === "h2000".U) & (addrw(10,0) === cReg.smTrigLen(3) - 1.U) io.uSMenq(1) := isEnW & (( addrw & "hF800".U ) === "h2000".U) & (addrw(10,0) === cReg.smTrigLen(3) - 1.U)