From 688a8cc1bd51324689cc0c9edb1f69a629af1290 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Thu, 22 May 2025 19:43:49 +0800 Subject: [PATCH] =?UTF-8?q?1=E3=80=81=E8=B4=9F=E8=B4=9F=E5=BE=97=E6=AD=A3?= =?UTF-8?q?=EF=BC=8Cspi=E6=96=B9=E5=90=91=E8=AE=A9=E9=A2=9D=E5=A4=96?= =?UTF-8?q?=E5=A4=9A=E8=AF=BB=E7=9A=84=E4=B8=80=E6=8B=8D=E4=BD=9C=E4=B8=BA?= =?UTF-8?q?sm=E8=AF=BB=E5=8F=96=E5=88=87=E6=8D=A2=E7=9A=84=E5=BB=B6?= =?UTF-8?q?=E8=BF=9F=202=E3=80=81=E4=BF=AE=E5=A4=8D=E9=94=99=E8=AF=AF?= =?UTF-8?q?=E7=9A=84sm=E8=AF=BB=E5=88=87=E6=8D=A2=E5=9C=B0=E5=9D=80mask?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/Interface.scala | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala index 987e742..7a96341 100644 --- a/src/main/scala/backBoard/shin/Interface.scala +++ b/src/main/scala/backBoard/shin/Interface.scala @@ -591,10 +591,10 @@ trait InterfaceCheckSM{ this: InterfaceBase => io.sram_w(2).enw := isEnW & (( addrw & "hF800".U ) === "h3000".U) io.sram_w(3).enw := isEnW & (( addrw & "hF800".U ) === "h4000".U) - io.dSMdeq(0) := isEnR & (( addrr & "hF800".U ) === "h0800".U) & (addrr(10,0) === cReg.smTrigLen(0) - 1.U) - io.dSMdeq(1) := isEnR & (( addrr & "hF800".U ) === "h0800".U) & (addrr(10,0) === cReg.smTrigLen(2) - 1.U) - io.dSMdeq(2) := isEnR & (( addrr & "hF800".U ) === "h0800".U) & (addrr(10,0) === cReg.smTrigLen(4) - 1.U) - io.dSMdeq(3) := isEnR & (( addrr & "hF800".U ) === "h0800".U) & (addrr(10,0) === cReg.smTrigLen(6) - 1.U) + io.dSMdeq(0) := isEnR & (( addrr & "hF800".U ) === "h0800".U) & (addrr(10,0) === cReg.smTrigLen(0) - 1.U + 1.U) + io.dSMdeq(1) := isEnR & (( addrr & "hF800".U ) === "h1800".U) & (addrr(10,0) === cReg.smTrigLen(2) - 1.U + 1.U) + io.dSMdeq(2) := isEnR & (( addrr & "hF800".U ) === "h2800".U) & (addrr(10,0) === cReg.smTrigLen(4) - 1.U + 1.U) + io.dSMdeq(3) := isEnR & (( addrr & "hF800".U ) === "h3800".U) & (addrr(10,0) === cReg.smTrigLen(6) - 1.U + 1.U) io.uSMenq(0) := isEnW & (( addrw & "hF800".U ) === "h1000".U) & (addrw(10,0) === cReg.smTrigLen(1) - 1.U) io.uSMenq(1) := isEnW & (( addrw & "hF800".U ) === "h2000".U) & (addrw(10,0) === cReg.smTrigLen(3) - 1.U)