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RuigeLee
2024-10-29 11:21:04 +08:00
parent 8068a31e77
commit 683b6cad92
7 changed files with 268 additions and 44 deletions
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144
tb/backSys_tb.v
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@@ -12,22 +12,87 @@ module backSys_TB (
reg overCLK;
wire io_uDatIn;
wire io_uDatOut;
wire io_dDatIn;
wire io_dDatOut;
wire [3:0] io_uDat;
wire [3:0] io_dDat;
wire [3:0] isLast;
BackSys s_BackSys(
BackSys s_Mst(
.clock(clock),
.reset(reset),
.io_overCLK(overCLK),
.io_uDatIn(io_uDatIn),
.io_uDatOut(io_uDatOut),
.io_dDatIn(io_dDatIn),
.io_dDatOut(io_dDatOut)
.io_uDatIn(io_uDat[0]),
.io_uDatOut(),
.io_dDatIn(1'b0),
.io_dDatOut(io_dDat[0]),
.io_out(),
.io_in(32'b0),
.io_isOnline(),
.io_isLast(isLast[0]),
.io_DCIn(1'b0)
);
BackSys s_Slv0(
.clock(clock),
.reset(reset),
.io_overCLK(overCLK),
.io_uDatIn(io_uDat[1]),
.io_uDatOut(io_uDat[0]),
.io_dDatIn(io_dDat[0]),
.io_dDatOut(io_dDat[1]),
.io_out(),
.io_in(32'b0),
.io_isOnline(isLast[0]),
.io_isLast(isLast[1]),
.io_DCIn(1'b0)
);
BackSys s_Slv1(
.clock(clock),
.reset(reset),
.io_overCLK(overCLK),
.io_uDatIn(io_uDat[2]),
.io_uDatOut(io_uDat[1]),
.io_dDatIn(io_dDat[1]),
.io_dDatOut(io_dDat[2]),
.io_out(),
.io_in(32'b0),
.io_isOnline(isLast[1]),
.io_isLast(isLast[2]),
.io_DCIn(1'b0)
);
BackSys s_Slv2(
.clock(clock),
.reset(reset),
.io_overCLK(overCLK),
.io_uDatIn(io_uDat[3]),
.io_uDatOut(io_uDat[2]),
.io_dDatIn(io_dDat[2]),
.io_dDatOut(io_dDat[3]),
.io_out(),
.io_in(32'b0),
.io_isOnline(isLast[2]),
.io_isLast(isLast[3]),
.io_DCIn(1'b0)
);
BackSys s_Slv3(
.clock(clock),
.reset(reset),
.io_overCLK(overCLK),
.io_uDatIn(1'b0),
.io_uDatOut(io_uDat[3]),
.io_dDatIn(io_dDat[3]),
.io_dDatOut(),
.io_out(),
.io_in(32'b0),
.io_isOnline(isLast[3]),
.io_isLast(1'b1),
.io_DCIn(1'b0)
);
initial begin
@@ -54,18 +119,18 @@ initial begin
end
`define SRAM0 s_BackSys.sram.mem_0
`define SRAM1 s_BackSys.sram.mem_1
`define SRAM2 s_BackSys.sram.mem_2
`define SRAM3 s_BackSys.sram.mem_3
`define SRAM0 s_Mst.sram.mem_0
`define SRAM1 s_Mst.sram.mem_1
`define SRAM2 s_Mst.sram.mem_2
`define SRAM3 s_Mst.sram.mem_3
localparam DP = 2**14;
integer i, by;
integer i;
reg [7:0] mem [0:200000];
initial begin
$readmemh("./tb/sw/build/test.verilog", mem);
$readmemh("./tb/sw/build/mstTest.verilog", mem);
for ( i = 0; i < DP; i = i + 1 ) begin
`SRAM0[i] = | mem[i*4+0] ? mem[i*4+0]: 8'h0;
`SRAM1[i] = | mem[i*4+1] ? mem[i*4+1]: 8'h0;
@@ -74,10 +139,57 @@ end
// $display("ITCM %h: %h,%h", i*4,`SRAM_ODD.ram[i],`SRAM_EVE.ram[i]);
end
end
`define SLV0_SRAM0 s_Slv0.sram.mem_0
`define SLV0_SRAM1 s_Slv0.sram.mem_1
`define SLV0_SRAM2 s_Slv0.sram.mem_2
`define SLV0_SRAM3 s_Slv0.sram.mem_3
`define SLV1_SRAM0 s_Slv1.sram.mem_0
`define SLV1_SRAM1 s_Slv1.sram.mem_1
`define SLV1_SRAM2 s_Slv1.sram.mem_2
`define SLV1_SRAM3 s_Slv1.sram.mem_3
`define SLV2_SRAM0 s_Slv2.sram.mem_0
`define SLV2_SRAM1 s_Slv2.sram.mem_1
`define SLV2_SRAM2 s_Slv2.sram.mem_2
`define SLV2_SRAM3 s_Slv2.sram.mem_3
`define SLV3_SRAM0 s_Slv3.sram.mem_0
`define SLV3_SRAM1 s_Slv3.sram.mem_1
`define SLV3_SRAM2 s_Slv3.sram.mem_2
`define SLV3_SRAM3 s_Slv3.sram.mem_3
localparam DPS = 2**14;
reg [7:0] mem1 [0:200000];
initial begin
$readmemh("./tb/sw/build/slvTest.verilog", mem);
for ( i = 0; i < DP; i = i + 1 ) begin
`SLV0_SRAM0[i] = | mem[i*4+0] ? mem[i*4+0]: 8'h0;
`SLV0_SRAM1[i] = | mem[i*4+1] ? mem[i*4+1]: 8'h0;
`SLV0_SRAM2[i] = | mem[i*4+2] ? mem[i*4+2]: 8'h0;
`SLV0_SRAM3[i] = | mem[i*4+3] ? mem[i*4+3]: 8'h0;
`SLV1_SRAM0[i] = | mem[i*4+0] ? mem[i*4+0]: 8'h0;
`SLV1_SRAM1[i] = | mem[i*4+1] ? mem[i*4+1]: 8'h0;
`SLV1_SRAM2[i] = | mem[i*4+2] ? mem[i*4+2]: 8'h0;
`SLV1_SRAM3[i] = | mem[i*4+3] ? mem[i*4+3]: 8'h0;
`SLV2_SRAM0[i] = | mem[i*4+0] ? mem[i*4+0]: 8'h0;
`SLV2_SRAM1[i] = | mem[i*4+1] ? mem[i*4+1]: 8'h0;
`SLV2_SRAM2[i] = | mem[i*4+2] ? mem[i*4+2]: 8'h0;
`SLV2_SRAM3[i] = | mem[i*4+3] ? mem[i*4+3]: 8'h0;
`SLV3_SRAM0[i] = | mem[i*4+0] ? mem[i*4+0]: 8'h0;
`SLV3_SRAM1[i] = | mem[i*4+1] ? mem[i*4+1]: 8'h0;
`SLV3_SRAM2[i] = | mem[i*4+2] ? mem[i*4+2]: 8'h0;
`SLV3_SRAM3[i] = | mem[i*4+3] ? mem[i*4+3]: 8'h0;
// $display("ITCM %h: %h,%h", i*4,`SRAM_ODD.ram[i],`SRAM_EVE.ram[i]);
end
end
initial
begin

0
tb/sw/src/main.c → tb/sw/src/main.c.bk
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0
tb/sw/src/main.S → tb/sw/src/mstMain.S
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0
tb/sw/src/startup.S → tb/sw/src/mstStartup.S
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49
tb/sw/src/slvMain.S Normal file
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@@ -0,0 +1,49 @@
#define cdr_0_tx_status 0x40000000
#define cdr_0_tx_txLen 0x40000004
#define cdr_0_tx_txFifo 0x40000008
#define cdr_0_rx_softReset 0x40000010
#define cdr_0_rx_status 0x40000014
#define cdr_0_rx_rxLen 0x40000018
#define cdr_0_rx_rxFifo 0x4000001c
#define cdr_1_tx_status 0x40000080
#define cdr_1_tx_txLen 0x40000084
#define cdr_1_tx_txFifo 0x40000088
#define cdr_1_rx_softReset 0x40000090
#define cdr_1_rx_status 0x40000094
#define cdr_1_rx_rxLen 0x40000098
#define cdr_1_rx_rxFifo 0x4000009c
.global main
main:
lui x5, %hi(cdr_0_tx_status)
li x6, 128
sw x6, 4(x5) #cdr_0_tx_txLen
li x6, 32 # 设置循环次数
1:
beqz x15, 3f # 如果x10为0，则跳到3
2:
li x15, 0 # 清标志位
lw x7, 0(x5) # 读取cdr_0_tx_status的值
andi x7, x7, 0x2 # 检查第1比特（位1）
bnez x7, 2b # 如果第1比特不为0，则回到2处继续循环
3:
# 向cdr_0_tx_txFifo地址写入0x55，循环32次
sw x6, 8(x5) # 向cdr_0_tx_txFifo写入0x55
addi x6, x6, -1 # 递减计数器
bnez x6, 1b # 如果计数器不为0，则继续循环
4:
j 4b

54
tb/sw/src/slvStartup.S Normal file
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@@ -0,0 +1,54 @@
#include "custom_ops.S"
.extern main
.globl _prog_start
.section .text.init
_prog_start:
li x15, 0
picorv32_maskirq_insn(zero, zero)
call main
li gp, 1;
ecall
.balign 32
.section .trap_entry, "ax", %progbits
trap_entry:
# q0 return address
# q1 bitmask of all IRQ to be handled, may be more than one IRQ
# q2 q3 unused, can be use as temp storage register
# q寄存器已经禁用， Without the q-registers, the irq return address will be stored in x3 (gp) and the IRQ bitmask in x4 (tp),
addi x15, x4, 0
picorv32_retirq_insn()