202 lines
4.1 KiB
Verilog
202 lines
4.1 KiB
Verilog
`timescale 1 ns / 1 ps
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module backSys_TB (
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);
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reg clock;
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reg reset;
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reg overCLK;
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wire [3:0] io_uDat;
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wire [3:0] io_dDat;
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wire [3:0] isLast;
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BackSys s_Mst(
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.clock(clock),
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.reset(reset),
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.io_overCLK(overCLK),
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.io_uDatIn(io_uDat[0]),
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.io_uDatOut(),
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.io_dDatIn(1'b0),
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.io_dDatOut(io_dDat[0]),
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.io_out(),
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.io_in(32'b0),
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.io_isOnline(),
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.io_isLast(isLast[0]),
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.io_DCIn(1'b0)
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);
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BackSys s_Slv0(
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.clock(clock),
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.reset(reset),
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.io_overCLK(overCLK),
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.io_uDatIn(io_uDat[1]),
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.io_uDatOut(io_uDat[0]),
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.io_dDatIn(io_dDat[0]),
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.io_dDatOut(io_dDat[1]),
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.io_out(),
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.io_in(32'b0),
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.io_isOnline(isLast[0]),
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.io_isLast(isLast[1]),
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.io_DCIn(1'b0)
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);
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BackSys s_Slv1(
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.clock(clock),
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.reset(reset),
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.io_overCLK(overCLK),
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.io_uDatIn(io_uDat[2]),
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.io_uDatOut(io_uDat[1]),
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.io_dDatIn(io_dDat[1]),
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.io_dDatOut(io_dDat[2]),
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.io_out(),
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.io_in(32'b0),
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.io_isOnline(isLast[1]),
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.io_isLast(isLast[2]),
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.io_DCIn(1'b0)
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);
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BackSys s_Slv2(
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.clock(clock),
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.reset(reset),
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.io_overCLK(overCLK),
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.io_uDatIn(io_uDat[3]),
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.io_uDatOut(io_uDat[2]),
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.io_dDatIn(io_dDat[2]),
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.io_dDatOut(io_dDat[3]),
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.io_out(),
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.io_in(32'b0),
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.io_isOnline(isLast[2]),
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.io_isLast(isLast[3]),
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.io_DCIn(1'b0)
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);
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BackSys s_Slv3(
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.clock(clock),
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.reset(reset),
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.io_overCLK(overCLK),
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.io_uDatIn(1'b0),
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.io_uDatOut(io_uDat[3]),
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.io_dDatIn(io_dDat[3]),
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.io_dDatOut(),
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.io_out(),
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.io_in(32'b0),
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.io_isOnline(isLast[3]),
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.io_isLast(1'b1),
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.io_DCIn(1'b0)
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);
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initial begin
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clock = 0;
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reset = 1;
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overCLK = 0;
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#200
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reset <= 0;
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#160000
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$display("Time Out !!!");
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$stop;
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end
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initial begin
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forever begin #40 clock <= ~clock; end
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end
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initial begin
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forever begin #10 overCLK <= ~overCLK; end
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end
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`define SRAM0 s_Mst.sram.mem_0
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`define SRAM1 s_Mst.sram.mem_1
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`define SRAM2 s_Mst.sram.mem_2
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`define SRAM3 s_Mst.sram.mem_3
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localparam DP = 2**14;
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integer i;
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reg [7:0] mem [0:200000];
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initial begin
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$readmemh("./tb/sw/build/mstTest.verilog", mem);
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for ( i = 0; i < DP; i = i + 1 ) begin
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`SRAM0[i] = | mem[i*4+0] ? mem[i*4+0]: 8'h0;
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`SRAM1[i] = | mem[i*4+1] ? mem[i*4+1]: 8'h0;
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`SRAM2[i] = | mem[i*4+2] ? mem[i*4+2]: 8'h0;
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`SRAM3[i] = | mem[i*4+3] ? mem[i*4+3]: 8'h0;
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// $display("ITCM %h: %h,%h", i*4,`SRAM_ODD.ram[i],`SRAM_EVE.ram[i]);
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end
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end
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`define SLV0_SRAM0 s_Slv0.sram.mem_0
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`define SLV0_SRAM1 s_Slv0.sram.mem_1
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`define SLV0_SRAM2 s_Slv0.sram.mem_2
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`define SLV0_SRAM3 s_Slv0.sram.mem_3
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`define SLV1_SRAM0 s_Slv1.sram.mem_0
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`define SLV1_SRAM1 s_Slv1.sram.mem_1
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`define SLV1_SRAM2 s_Slv1.sram.mem_2
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`define SLV1_SRAM3 s_Slv1.sram.mem_3
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`define SLV2_SRAM0 s_Slv2.sram.mem_0
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`define SLV2_SRAM1 s_Slv2.sram.mem_1
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`define SLV2_SRAM2 s_Slv2.sram.mem_2
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`define SLV2_SRAM3 s_Slv2.sram.mem_3
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`define SLV3_SRAM0 s_Slv3.sram.mem_0
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`define SLV3_SRAM1 s_Slv3.sram.mem_1
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`define SLV3_SRAM2 s_Slv3.sram.mem_2
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`define SLV3_SRAM3 s_Slv3.sram.mem_3
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localparam DPS = 2**14;
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reg [7:0] mem1 [0:200000];
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initial begin
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$readmemh("./tb/sw/build/slvTest.verilog", mem);
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for ( i = 0; i < DP; i = i + 1 ) begin
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`SLV0_SRAM0[i] = | mem[i*4+0] ? mem[i*4+0]: 8'h0;
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`SLV0_SRAM1[i] = | mem[i*4+1] ? mem[i*4+1]: 8'h0;
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`SLV0_SRAM2[i] = | mem[i*4+2] ? mem[i*4+2]: 8'h0;
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`SLV0_SRAM3[i] = | mem[i*4+3] ? mem[i*4+3]: 8'h0;
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`SLV1_SRAM0[i] = | mem[i*4+0] ? mem[i*4+0]: 8'h0;
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`SLV1_SRAM1[i] = | mem[i*4+1] ? mem[i*4+1]: 8'h0;
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`SLV1_SRAM2[i] = | mem[i*4+2] ? mem[i*4+2]: 8'h0;
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`SLV1_SRAM3[i] = | mem[i*4+3] ? mem[i*4+3]: 8'h0;
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`SLV2_SRAM0[i] = | mem[i*4+0] ? mem[i*4+0]: 8'h0;
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`SLV2_SRAM1[i] = | mem[i*4+1] ? mem[i*4+1]: 8'h0;
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`SLV2_SRAM2[i] = | mem[i*4+2] ? mem[i*4+2]: 8'h0;
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`SLV2_SRAM3[i] = | mem[i*4+3] ? mem[i*4+3]: 8'h0;
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`SLV3_SRAM0[i] = | mem[i*4+0] ? mem[i*4+0]: 8'h0;
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`SLV3_SRAM1[i] = | mem[i*4+1] ? mem[i*4+1]: 8'h0;
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`SLV3_SRAM2[i] = | mem[i*4+2] ? mem[i*4+2]: 8'h0;
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`SLV3_SRAM3[i] = | mem[i*4+3] ? mem[i*4+3]: 8'h0;
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// $display("ITCM %h: %h,%h", i*4,`SRAM_ODD.ram[i],`SRAM_EVE.ram[i]);
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end
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end
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initial
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begin
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$dumpfile("./build/wave.vcd"); //生成的vcd文件名称
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$dumpvars(0, backSys_TB);//tb模块名称
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end
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endmodule
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