ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

错误写入SRAM争夺了SRAM控制权：CRC操作并入传输，CDR错误仅用上升沿触发

Browse Source
This commit is contained in:
RuigeLee
2024-05-23 13:44:19 +08:00
parent 99525c4f01
commit 67bfafd0df
1 changed files with 33 additions and 26 deletions
Download Patch File Download Diff File Expand all files Collapse all files

39
src/main/scala/backBoard/BackBoardMst.scala
View File

@@ -438,6 +438,15 @@ trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>
when( io.lvdsMst.upstream_crc_valid ){
stateCur := 7.U
when( io.lvdsMst.upstream_crc_err ){
mirrorReg.io.addrB := STATUSCRCERRADDR
mirrorReg.io.datawB := 1.U
mirrorReg.io.enwB := true.B
}
}
} .elsewhen( stateCur === 7.U ){
stateCur := 8.U
//statusTransmit
mirrorReg.io.addrB := STATUSTRANSADDR
mirrorReg.io.datawB := 1.U
@@ -445,10 +454,7 @@ trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>
ctrlTransmit := false.B
interrupt := true.B
}
} .elsewhen( stateCur === 7.U ){
// stateCur := 8.U
}.elsewhen( stateCur === 8.U ){
} .otherwise{
@@ -523,6 +529,16 @@ trait BackBoardMstLVDSUnicast{ this: BackBoardMstLVDSBase =>
when( io.lvdsMst.upstream_crc_valid ){
stateCur := 7.U
when( io.lvdsMst.upstream_crc_err ){
mirrorReg.io.addrB := STATUSCRCERRADDR
mirrorReg.io.datawB := 1.U
mirrorReg.io.enwB := true.B
}
}
} .elsewhen( stateCur === 7.U ){
stateCur := 8.U
//statusUnicast
mirrorReg.io.addrB := STATUSUNICASTADDR
mirrorReg.io.datawB := 1.U
@@ -530,10 +546,8 @@ trait BackBoardMstLVDSUnicast{ this: BackBoardMstLVDSBase =>
ctrlUnicast := false.B
interrupt := true.B
}
} .elsewhen( stateCur === 7.U ){
// stateCur := 8.U
} .elsewhen( stateCur === 8.U ){
} .otherwise{
@@ -581,21 +595,14 @@ trait BackBoardMstLVDSError{ this: BackBoardMstLVDSBase =>
when( io.lvdsMst.upstream_cdr_err ){
val shiftCDRErr = ShiftRegisters( io.lvdsMst.upstream_cdr_err, 2, false.B, true.B )
when( ~shiftCDRErr(0) & io.lvdsMst.upstream_cdr_err ){
mirrorReg.io.addrB := STATUSCDRERRADDR
mirrorReg.io.datawB := 1.U
mirrorReg.io.enwB := true.B
interrupt := true.B
}
when( io.lvdsMst.upstream_crc_valid & io.lvdsMst.upstream_crc_err ){
mirrorReg.io.addrB := STATUSCRCERRADDR
mirrorReg.io.datawB := 1.U
mirrorReg.io.enwB := true.B
interrupt := true.B
}
}
class BackBoardMst extends BackBoardMstLVDSBase