From 67bfafd0dfa14272290f4b9b9772b1e87e5c74a5 Mon Sep 17 00:00:00 2001
From: RuigeLee <wut.ruigeli@gmail.com>
Date: Thu, 23 May 2024 13:44:19 +0800
Subject: [PATCH] =?UTF-8?q?=E9=94=99=E8=AF=AF=E5=86=99=E5=85=A5SRAM?=
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---
 src/main/scala/backBoard/BackBoardMst.scala | 59 ++++++++++++---------
 1 file changed, 33 insertions(+), 26 deletions(-)

diff --git a/src/main/scala/backBoard/BackBoardMst.scala b/src/main/scala/backBoard/BackBoardMst.scala
index 5c481f4..88aaf44 100644
--- a/src/main/scala/backBoard/BackBoardMst.scala
+++ b/src/main/scala/backBoard/BackBoardMst.scala
@@ -438,17 +438,23 @@ trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>
       when( io.lvdsMst.upstream_crc_valid ){
         stateCur := 7.U
 
-        //statusTransmit
-        mirrorReg.io.addrB  := STATUSTRANSADDR
-        mirrorReg.io.datawB := 1.U
-        mirrorReg.io.enwB   := true.B
-
-        ctrlTransmit := false.B
-        interrupt    := true.B
+        when( io.lvdsMst.upstream_crc_err ){
+          mirrorReg.io.addrB  := STATUSCRCERRADDR
+          mirrorReg.io.datawB := 1.U
+          mirrorReg.io.enwB   := true.B            
+        }
       }
-
     } .elsewhen( stateCur === 7.U ){  
-      // stateCur := 8.U
+      stateCur := 8.U
+
+      //statusTransmit
+      mirrorReg.io.addrB  := STATUSTRANSADDR
+      mirrorReg.io.datawB := 1.U
+      mirrorReg.io.enwB   := true.B
+
+      ctrlTransmit := false.B
+      interrupt    := true.B
+    }.elsewhen( stateCur === 8.U ){
 
     } .otherwise{
 
@@ -523,17 +529,25 @@ trait BackBoardMstLVDSUnicast{ this: BackBoardMstLVDSBase =>
       when( io.lvdsMst.upstream_crc_valid ){
         stateCur := 7.U
 
-        //statusUnicast
-        mirrorReg.io.addrB  := STATUSUNICASTADDR
-        mirrorReg.io.datawB := 1.U
-        mirrorReg.io.enwB   := true.B
+        when( io.lvdsMst.upstream_crc_err ){
+          mirrorReg.io.addrB  := STATUSCRCERRADDR
+          mirrorReg.io.datawB := 1.U
+          mirrorReg.io.enwB   := true.B            
+        }
 
-        ctrlUnicast := false.B
-        interrupt    := true.B
       }
+    } .elsewhen( stateCur === 7.U ){
+      stateCur := 8.U
 
-    } .elsewhen( stateCur === 7.U ){  
-      // stateCur := 8.U
+      //statusUnicast
+      mirrorReg.io.addrB  := STATUSUNICASTADDR
+      mirrorReg.io.datawB := 1.U
+      mirrorReg.io.enwB   := true.B
+
+      ctrlUnicast := false.B
+      interrupt   := true.B
+
+    } .elsewhen( stateCur === 8.U ){
 
     } .otherwise{
 
@@ -581,21 +595,14 @@ trait BackBoardMstLVDSError{ this: BackBoardMstLVDSBase =>
 
 
 
-
-  when( io.lvdsMst.upstream_cdr_err ){
+  val shiftCDRErr = ShiftRegisters( io.lvdsMst.upstream_cdr_err, 2, false.B, true.B )
+  when( ~shiftCDRErr(0) & io.lvdsMst.upstream_cdr_err ){
     mirrorReg.io.addrB  := STATUSCDRERRADDR
     mirrorReg.io.datawB := 1.U
     mirrorReg.io.enwB   := true.B   
     interrupt     := true.B
   }
 
-  when( io.lvdsMst.upstream_crc_valid & io.lvdsMst.upstream_crc_err ){
-    mirrorReg.io.addrB  := STATUSCRCERRADDR
-    mirrorReg.io.datawB := 1.U
-    mirrorReg.io.enwB   := true.B   
-    interrupt     := true.B
-  }
-
 }
 
 class BackBoardMst extends BackBoardMstLVDSBase