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错误写入SRAM争夺了SRAM控制权：CRC操作并入传输，CDR错误仅用上升沿触发

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This commit is contained in:
RuigeLee
2024-05-23 13:44:19 +08:00
parent 99525c4f01
commit 67bfafd0df
1 changed files with 33 additions and 26 deletions
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59
src/main/scala/backBoard/BackBoardMst.scala
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@@ -438,17 +438,23 @@ trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>
when( io.lvdsMst.upstream_crc_valid ){ when( io.lvdsMst.upstream_crc_valid ){
stateCur := 7.U stateCur := 7.U
//statusTransmit when( io.lvdsMst.upstream_crc_err ){
mirrorReg.io.addrB := STATUSTRANSADDR mirrorReg.io.addrB := STATUSCRCERRADDR
mirrorReg.io.datawB := 1.U mirrorReg.io.datawB := 1.U
mirrorReg.io.enwB := true.B mirrorReg.io.enwB := true.B
}
ctrlTransmit := false.B
interrupt := true.B
} }
} .elsewhen( stateCur === 7.U ){ } .elsewhen( stateCur === 7.U ){
// stateCur := 8.U stateCur := 8.U
//statusTransmit
mirrorReg.io.addrB := STATUSTRANSADDR
mirrorReg.io.datawB := 1.U
mirrorReg.io.enwB := true.B
ctrlTransmit := false.B
interrupt := true.B
}.elsewhen( stateCur === 8.U ){
} .otherwise{ } .otherwise{
@@ -523,17 +529,25 @@ trait BackBoardMstLVDSUnicast{ this: BackBoardMstLVDSBase =>
when( io.lvdsMst.upstream_crc_valid ){ when( io.lvdsMst.upstream_crc_valid ){
stateCur := 7.U stateCur := 7.U
//statusUnicast when( io.lvdsMst.upstream_crc_err ){
mirrorReg.io.addrB := STATUSUNICASTADDR mirrorReg.io.addrB := STATUSCRCERRADDR
mirrorReg.io.datawB := 1.U mirrorReg.io.datawB := 1.U
mirrorReg.io.enwB := true.B mirrorReg.io.enwB := true.B
}
ctrlUnicast := false.B
interrupt := true.B
} }
} .elsewhen( stateCur === 7.U ){
stateCur := 8.U
} .elsewhen( stateCur === 7.U ){ //statusUnicast
// stateCur := 8.U mirrorReg.io.addrB := STATUSUNICASTADDR
mirrorReg.io.datawB := 1.U
mirrorReg.io.enwB := true.B
ctrlUnicast := false.B
interrupt := true.B
} .elsewhen( stateCur === 8.U ){
} .otherwise{ } .otherwise{
@@ -581,21 +595,14 @@ trait BackBoardMstLVDSError{ this: BackBoardMstLVDSBase =>
val shiftCDRErr = ShiftRegisters( io.lvdsMst.upstream_cdr_err, 2, false.B, true.B )
when( io.lvdsMst.upstream_cdr_err ){ when( ~shiftCDRErr(0) & io.lvdsMst.upstream_cdr_err ){
mirrorReg.io.addrB := STATUSCDRERRADDR mirrorReg.io.addrB := STATUSCDRERRADDR
mirrorReg.io.datawB := 1.U mirrorReg.io.datawB := 1.U
mirrorReg.io.enwB := true.B mirrorReg.io.enwB := true.B
interrupt := true.B interrupt := true.B
} }
when( io.lvdsMst.upstream_crc_valid & io.lvdsMst.upstream_crc_err ){
mirrorReg.io.addrB := STATUSCRCERRADDR
mirrorReg.io.datawB := 1.U
mirrorReg.io.enwB := true.B
interrupt := true.B
}
} }
class BackBoardMst extends BackBoardMstLVDSBase class BackBoardMst extends BackBoardMstLVDSBase