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链接地址到4kw，4rocket联合仿真

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This commit is contained in:
Ruige Lee
2025-01-15 11:21:44 +08:00
parent fef7acb54a
commit 65c9c746a2
2 changed files with 218 additions and 41 deletions
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4
tb/sw/linker.lds
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@@ -2,7 +2,7 @@ ENTRY(_prog_start)
SECTIONS SECTIONS
{ {
RAM_BASE = 0x80000000; RAM_BASE = 0x40000000;
. = RAM_BASE; . = RAM_BASE;
@@ -37,6 +37,6 @@ SECTIONS
_RODATA_END_ = .; _RODATA_END_ = .;
} }
. = 0x80000800; . = 0x40000800;
.trap_entry : { *(.trap_entry)} .trap_entry : { *(.trap_entry)}
} }

255
tb/verilator/SimTop.v
View File

@@ -13,23 +13,22 @@ module SimTop (
input clock, //100MHz input clock, //100MHz
input reset, input reset,
input clk400, input clk400
input uDatIn,
output uDatOut,
input dDatIn,
output dDatOut
); );
wire [3:0] uDatSer;
wire [3:0] dDatSer;
wire dmactive; wire [3:0] dmactive;
ExampleRocketSystem s_rocket( ExampleRocketSystem s_rocket_mst(
.clock(clock), .clock(clock),
.reset(reset), .reset(reset),
.resetctrl_hartIsInReset_0(reset), .resetctrl_hartIsInReset_0(reset),
@@ -46,8 +45,8 @@ ExampleRocketSystem s_rocket(
.debug_systemjtag_part_number(16'b0), .debug_systemjtag_part_number(16'b0),
.debug_systemjtag_version(4'b0), .debug_systemjtag_version(4'b0),
.debug_ndreset(), .debug_ndreset(),
.debug_dmactive(dmactive), .debug_dmactive(dmactive[0]),
.debug_dmactiveAck(dmactive), .debug_dmactiveAck(dmactive[0]),
.mmio_apb_0_psel(), .mmio_apb_0_psel(),
.mmio_apb_0_penable(), .mmio_apb_0_penable(),
@@ -79,13 +78,183 @@ ExampleRocketSystem s_rocket(
.interrupts(2'b0), .interrupts(2'b0),
.cdrio_overCLK(clk400), .cdrio_overCLK(clk400),
.cdrio_uDatIn(uDatIn), .cdrio_uDatIn(uDatSer[0]),
.cdrio_uDatOut(uDatOut), .cdrio_uDatOut(),
.cdrio_dDatIn(dDatIn), .cdrio_dDatIn(1'b0),
.cdrio_dDatOut(dDatOut) .cdrio_dDatOut(dDatSer[0])
); );
ExampleRocketSystem s_rocket_slv0(
.clock(clock),
.reset(reset),
.resetctrl_hartIsInReset_0(reset),
.debug_clock(clock),
.debug_reset(reset),
.debug_systemjtag_jtag_TCK(1'b0),
.debug_systemjtag_jtag_TMS(1'b0),
.debug_systemjtag_jtag_TDI(1'b0),
.debug_systemjtag_jtag_TDO_data(),
.debug_systemjtag_jtag_TDO_driven(),
.debug_systemjtag_reset(reset),
.debug_systemjtag_mfr_id(11'b0),
.debug_systemjtag_part_number(16'b0),
.debug_systemjtag_version(4'b0),
.debug_ndreset(),
.debug_dmactive(dmactive[1]),
.debug_dmactiveAck(dmactive[1]),
.mmio_apb_0_psel(),
.mmio_apb_0_penable(),
.mmio_apb_0_pwrite(),
.mmio_apb_0_paddr(),
.mmio_apb_0_pprot(),
.mmio_apb_0_pwdata(),
.mmio_apb_0_pstrb(),
.mmio_apb_0_pready(1'b1),
.mmio_apb_0_pslverr(1'b0),
.mmio_apb_0_prdata(32'b0),
.mmio_ahb_0_hmastlock(),
.mmio_ahb_0_hsel(),
.mmio_ahb_0_hready(),
.mmio_ahb_0_hreadyout(1'b1),
.mmio_ahb_0_htrans(),
.mmio_ahb_0_hsize(),
.mmio_ahb_0_hburst(),
.mmio_ahb_0_hwrite(),
.mmio_ahb_0_hprot(),
.mmio_ahb_0_haddr(),
.mmio_ahb_0_hwdata(),
.mmio_ahb_0_hresp(2'b0),
.mmio_ahb_0_hrdata(32'b0),
.mmio_ahb_0_hmaster(),
.mmio_ahb_0_hsplit(16'b0),
.interrupts(2'b0),
.cdrio_overCLK(clk400),
.cdrio_uDatIn(uDatSer[1]),
.cdrio_uDatOut(uDatSer[0]),
.cdrio_dDatIn(dDatSer[0]),
.cdrio_dDatOut(dDatSer[1])
);
ExampleRocketSystem s_rocket_slv1(
.clock(clock),
.reset(reset),
.resetctrl_hartIsInReset_0(reset),
.debug_clock(clock),
.debug_reset(reset),
.debug_systemjtag_jtag_TCK(1'b0),
.debug_systemjtag_jtag_TMS(1'b0),
.debug_systemjtag_jtag_TDI(1'b0),
.debug_systemjtag_jtag_TDO_data(),
.debug_systemjtag_jtag_TDO_driven(),
.debug_systemjtag_reset(reset),
.debug_systemjtag_mfr_id(11'b0),
.debug_systemjtag_part_number(16'b0),
.debug_systemjtag_version(4'b0),
.debug_ndreset(),
.debug_dmactive(dmactive[2]),
.debug_dmactiveAck(dmactive[2]),
.mmio_apb_0_psel(),
.mmio_apb_0_penable(),
.mmio_apb_0_pwrite(),
.mmio_apb_0_paddr(),
.mmio_apb_0_pprot(),
.mmio_apb_0_pwdata(),
.mmio_apb_0_pstrb(),
.mmio_apb_0_pready(1'b1),
.mmio_apb_0_pslverr(1'b0),
.mmio_apb_0_prdata(32'b0),
.mmio_ahb_0_hmastlock(),
.mmio_ahb_0_hsel(),
.mmio_ahb_0_hready(),
.mmio_ahb_0_hreadyout(1'b1),
.mmio_ahb_0_htrans(),
.mmio_ahb_0_hsize(),
.mmio_ahb_0_hburst(),
.mmio_ahb_0_hwrite(),
.mmio_ahb_0_hprot(),
.mmio_ahb_0_haddr(),
.mmio_ahb_0_hwdata(),
.mmio_ahb_0_hresp(2'b0),
.mmio_ahb_0_hrdata(32'b0),
.mmio_ahb_0_hmaster(),
.mmio_ahb_0_hsplit(16'b0),
.interrupts(2'b0),
.cdrio_overCLK(clk400),
.cdrio_uDatIn(uDatSer[2]),
.cdrio_uDatOut(uDatSer[1]),
.cdrio_dDatIn(dDatSer[1]),
.cdrio_dDatOut(dDatSer[2])
);
ExampleRocketSystem s_rocket_slv2(
.clock(clock),
.reset(reset),
.resetctrl_hartIsInReset_0(reset),
.debug_clock(clock),
.debug_reset(reset),
.debug_systemjtag_jtag_TCK(1'b0),
.debug_systemjtag_jtag_TMS(1'b0),
.debug_systemjtag_jtag_TDI(1'b0),
.debug_systemjtag_jtag_TDO_data(),
.debug_systemjtag_jtag_TDO_driven(),
.debug_systemjtag_reset(reset),
.debug_systemjtag_mfr_id(11'b0),
.debug_systemjtag_part_number(16'b0),
.debug_systemjtag_version(4'b0),
.debug_ndreset(),
.debug_dmactive(dmactive[3]),
.debug_dmactiveAck(dmactive[3]),
.mmio_apb_0_psel(),
.mmio_apb_0_penable(),
.mmio_apb_0_pwrite(),
.mmio_apb_0_paddr(),
.mmio_apb_0_pprot(),
.mmio_apb_0_pwdata(),
.mmio_apb_0_pstrb(),
.mmio_apb_0_pready(1'b1),
.mmio_apb_0_pslverr(1'b0),
.mmio_apb_0_prdata(32'b0),
.mmio_ahb_0_hmastlock(),
.mmio_ahb_0_hsel(),
.mmio_ahb_0_hready(),
.mmio_ahb_0_hreadyout(1'b1),
.mmio_ahb_0_htrans(),
.mmio_ahb_0_hsize(),
.mmio_ahb_0_hburst(),
.mmio_ahb_0_hwrite(),
.mmio_ahb_0_hprot(),
.mmio_ahb_0_haddr(),
.mmio_ahb_0_hwdata(),
.mmio_ahb_0_hresp(2'b0),
.mmio_ahb_0_hrdata(32'b0),
.mmio_ahb_0_hmaster(),
.mmio_ahb_0_hsplit(16'b0),
.interrupts(2'b0),
.cdrio_overCLK(clk400),
.cdrio_uDatIn(1'b0),
.cdrio_uDatOut(uDatSer[2]),
.cdrio_dDatIn(dDatSer[2]),
.cdrio_dDatOut()
);
@@ -144,7 +313,6 @@ ExampleRocketSystem s_rocket(
// assign success = debugger_success; // assign success = debugger_success;
@@ -152,8 +320,13 @@ ExampleRocketSystem s_rocket(
string testName; string testName;
`define MEM s_rocket.ram.Mem_SRAM.Mem_SRAM_ext.ram `define MEM0 s_rocket_mst.ram.Mem_SRAM.Mem_SRAM_ext.ram
reg [7:0] mem [0:200000]; `define MEM1 s_rocket_slv0.ram.Mem_SRAM.Mem_SRAM_ext.ram
`define MEM2 s_rocket_slv1.ram.Mem_SRAM.Mem_SRAM_ext.ram
`define MEM3 s_rocket_slv2.ram.Mem_SRAM.Mem_SRAM_ext.ram
reg [7:0] mem0 [0:200000];
reg [7:0] mem1 [0:200000];
localparam DP = 8192; localparam DP = 8192;
integer i; integer i;
@@ -161,36 +334,40 @@ initial begin
#20 #20
if ( $value$plusargs("%s",testName) ) begin // if ( $value$plusargs("%s",testName) ) begin
$display("%s",testName); // $display("%s",testName);
$readmemh(testName, mem); // $readmemh(testName, mem);
end // end
else begin // else begin
$display("%s",testName); // $display("%s",testName);
$error("Failed to read Files!"); // $error("Failed to read Files!");
end // end
$readmemh("./tb/sw/build/mstTest.verilog", mem0);
for ( i = 0; i < DP; i = i + 1 ) begin for ( i = 0; i < DP; i = i + 1 ) begin
if ( mem[i*4+0] || mem[i*4+1] || mem[i*4+2] || mem[i*4+3] ) begin if ( mem0[i*4+0] || mem0[i*4+1] || mem0[i*4+2] || mem0[i*4+3] ) begin
`MEM[i] = {mem[i*4+3], mem[i*4+2], mem[i*4+1], mem[i*4+0]}; `MEM0[i] = {mem0[i*4+3], mem0[i*4+2], mem0[i*4+1], mem0[i*4+0]};
$display("%x",`MEM[i]);
end end
else begin else begin
`MEM[i][7:0] = 8'h0; `MEM0[i] = 32'h0;
`MEM[i][15:8] = 8'h0;
`MEM[i][23:16] = 8'h0;
`MEM[i][31:24] = 8'h0;
end end
end end
end
wire [31:0] test1 = `MEM[0]; $readmemh("./tb/sw/build/slvTest.verilog", mem1);
wire [31:0] test2 = `MEM[1]; for ( i = 0; i < DP; i = i + 1 ) begin
wire [31:0] test3 = `MEM[2]; if ( mem1[i*4+0] || mem1[i*4+1] || mem1[i*4+2] || mem1[i*4+3] ) begin
wire [31:0] test4 = `MEM[3]; `MEM1[i] = {mem1[i*4+3], mem1[i*4+2], mem1[i*4+1], mem1[i*4+0]};
`MEM2[i] = {mem1[i*4+3], mem1[i*4+2], mem1[i*4+1], mem1[i*4+0]};
`MEM3[i] = {mem1[i*4+3], mem1[i*4+2], mem1[i*4+1], mem1[i*4+0]};
end
else begin
`MEM1[i] = 32'h0;
`MEM2[i] = 32'h0;
`MEM3[i] = 32'h0;
end
end
end