From 65c9c746a25fb62ae91e8e04915a3e2d8f610d25 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Wed, 15 Jan 2025 11:21:44 +0800 Subject: [PATCH] =?UTF-8?q?=E9=93=BE=E6=8E=A5=E5=9C=B0=E5=9D=80=E5=88=B04k?= =?UTF-8?q?w=EF=BC=8C4rocket=E8=81=94=E5=90=88=E4=BB=BF=E7=9C=9F?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- tb/sw/linker.lds | 4 +- tb/verilator/SimTop.v | 255 +++++++++++++++++++++++++++++++++++------- 2 files changed, 218 insertions(+), 41 deletions(-) diff --git a/tb/sw/linker.lds b/tb/sw/linker.lds index e918338..1ed3937 100644 --- a/tb/sw/linker.lds +++ b/tb/sw/linker.lds @@ -2,7 +2,7 @@ ENTRY(_prog_start) SECTIONS { - RAM_BASE = 0x80000000; + RAM_BASE = 0x40000000; . = RAM_BASE; @@ -37,6 +37,6 @@ SECTIONS _RODATA_END_ = .; } - . = 0x80000800; + . = 0x40000800; .trap_entry : { *(.trap_entry)} } diff --git a/tb/verilator/SimTop.v b/tb/verilator/SimTop.v index 758499d..65490d8 100644 --- a/tb/verilator/SimTop.v +++ b/tb/verilator/SimTop.v @@ -13,23 +13,22 @@ module SimTop ( input clock, //100MHz input reset, - input clk400, + input clk400 + - input uDatIn, - output uDatOut, - input dDatIn, - output dDatOut ); +wire [3:0] uDatSer; +wire [3:0] dDatSer; -wire dmactive; +wire [3:0] dmactive; -ExampleRocketSystem s_rocket( +ExampleRocketSystem s_rocket_mst( .clock(clock), .reset(reset), .resetctrl_hartIsInReset_0(reset), @@ -46,8 +45,8 @@ ExampleRocketSystem s_rocket( .debug_systemjtag_part_number(16'b0), .debug_systemjtag_version(4'b0), .debug_ndreset(), - .debug_dmactive(dmactive), - .debug_dmactiveAck(dmactive), + .debug_dmactive(dmactive[0]), + .debug_dmactiveAck(dmactive[0]), .mmio_apb_0_psel(), .mmio_apb_0_penable(), @@ -79,13 +78,183 @@ ExampleRocketSystem s_rocket( .interrupts(2'b0), .cdrio_overCLK(clk400), - .cdrio_uDatIn(uDatIn), - .cdrio_uDatOut(uDatOut), - .cdrio_dDatIn(dDatIn), - .cdrio_dDatOut(dDatOut) + .cdrio_uDatIn(uDatSer[0]), + .cdrio_uDatOut(), + .cdrio_dDatIn(1'b0), + .cdrio_dDatOut(dDatSer[0]) ); +ExampleRocketSystem s_rocket_slv0( + .clock(clock), + .reset(reset), + .resetctrl_hartIsInReset_0(reset), + + .debug_clock(clock), + .debug_reset(reset), + .debug_systemjtag_jtag_TCK(1'b0), + .debug_systemjtag_jtag_TMS(1'b0), + .debug_systemjtag_jtag_TDI(1'b0), + .debug_systemjtag_jtag_TDO_data(), + .debug_systemjtag_jtag_TDO_driven(), + .debug_systemjtag_reset(reset), + .debug_systemjtag_mfr_id(11'b0), + .debug_systemjtag_part_number(16'b0), + .debug_systemjtag_version(4'b0), + .debug_ndreset(), + .debug_dmactive(dmactive[1]), + .debug_dmactiveAck(dmactive[1]), + + .mmio_apb_0_psel(), + .mmio_apb_0_penable(), + .mmio_apb_0_pwrite(), + .mmio_apb_0_paddr(), + .mmio_apb_0_pprot(), + .mmio_apb_0_pwdata(), + .mmio_apb_0_pstrb(), + .mmio_apb_0_pready(1'b1), + .mmio_apb_0_pslverr(1'b0), + .mmio_apb_0_prdata(32'b0), + + .mmio_ahb_0_hmastlock(), + .mmio_ahb_0_hsel(), + .mmio_ahb_0_hready(), + .mmio_ahb_0_hreadyout(1'b1), + .mmio_ahb_0_htrans(), + .mmio_ahb_0_hsize(), + .mmio_ahb_0_hburst(), + .mmio_ahb_0_hwrite(), + .mmio_ahb_0_hprot(), + .mmio_ahb_0_haddr(), + .mmio_ahb_0_hwdata(), + .mmio_ahb_0_hresp(2'b0), + .mmio_ahb_0_hrdata(32'b0), + .mmio_ahb_0_hmaster(), + .mmio_ahb_0_hsplit(16'b0), + + .interrupts(2'b0), + + .cdrio_overCLK(clk400), + .cdrio_uDatIn(uDatSer[1]), + .cdrio_uDatOut(uDatSer[0]), + .cdrio_dDatIn(dDatSer[0]), + .cdrio_dDatOut(dDatSer[1]) +); + + +ExampleRocketSystem s_rocket_slv1( + .clock(clock), + .reset(reset), + .resetctrl_hartIsInReset_0(reset), + + .debug_clock(clock), + .debug_reset(reset), + .debug_systemjtag_jtag_TCK(1'b0), + .debug_systemjtag_jtag_TMS(1'b0), + .debug_systemjtag_jtag_TDI(1'b0), + .debug_systemjtag_jtag_TDO_data(), + .debug_systemjtag_jtag_TDO_driven(), + .debug_systemjtag_reset(reset), + .debug_systemjtag_mfr_id(11'b0), + .debug_systemjtag_part_number(16'b0), + .debug_systemjtag_version(4'b0), + .debug_ndreset(), + .debug_dmactive(dmactive[2]), + .debug_dmactiveAck(dmactive[2]), + + .mmio_apb_0_psel(), + .mmio_apb_0_penable(), + .mmio_apb_0_pwrite(), + .mmio_apb_0_paddr(), + .mmio_apb_0_pprot(), + .mmio_apb_0_pwdata(), + .mmio_apb_0_pstrb(), + .mmio_apb_0_pready(1'b1), + .mmio_apb_0_pslverr(1'b0), + .mmio_apb_0_prdata(32'b0), + + .mmio_ahb_0_hmastlock(), + .mmio_ahb_0_hsel(), + .mmio_ahb_0_hready(), + .mmio_ahb_0_hreadyout(1'b1), + .mmio_ahb_0_htrans(), + .mmio_ahb_0_hsize(), + .mmio_ahb_0_hburst(), + .mmio_ahb_0_hwrite(), + .mmio_ahb_0_hprot(), + .mmio_ahb_0_haddr(), + .mmio_ahb_0_hwdata(), + .mmio_ahb_0_hresp(2'b0), + .mmio_ahb_0_hrdata(32'b0), + .mmio_ahb_0_hmaster(), + .mmio_ahb_0_hsplit(16'b0), + + .interrupts(2'b0), + + .cdrio_overCLK(clk400), + .cdrio_uDatIn(uDatSer[2]), + .cdrio_uDatOut(uDatSer[1]), + .cdrio_dDatIn(dDatSer[1]), + .cdrio_dDatOut(dDatSer[2]) +); + + +ExampleRocketSystem s_rocket_slv2( + .clock(clock), + .reset(reset), + .resetctrl_hartIsInReset_0(reset), + + .debug_clock(clock), + .debug_reset(reset), + .debug_systemjtag_jtag_TCK(1'b0), + .debug_systemjtag_jtag_TMS(1'b0), + .debug_systemjtag_jtag_TDI(1'b0), + .debug_systemjtag_jtag_TDO_data(), + .debug_systemjtag_jtag_TDO_driven(), + .debug_systemjtag_reset(reset), + .debug_systemjtag_mfr_id(11'b0), + .debug_systemjtag_part_number(16'b0), + .debug_systemjtag_version(4'b0), + .debug_ndreset(), + .debug_dmactive(dmactive[3]), + .debug_dmactiveAck(dmactive[3]), + + .mmio_apb_0_psel(), + .mmio_apb_0_penable(), + .mmio_apb_0_pwrite(), + .mmio_apb_0_paddr(), + .mmio_apb_0_pprot(), + .mmio_apb_0_pwdata(), + .mmio_apb_0_pstrb(), + .mmio_apb_0_pready(1'b1), + .mmio_apb_0_pslverr(1'b0), + .mmio_apb_0_prdata(32'b0), + + .mmio_ahb_0_hmastlock(), + .mmio_ahb_0_hsel(), + .mmio_ahb_0_hready(), + .mmio_ahb_0_hreadyout(1'b1), + .mmio_ahb_0_htrans(), + .mmio_ahb_0_hsize(), + .mmio_ahb_0_hburst(), + .mmio_ahb_0_hwrite(), + .mmio_ahb_0_hprot(), + .mmio_ahb_0_haddr(), + .mmio_ahb_0_hwdata(), + .mmio_ahb_0_hresp(2'b0), + .mmio_ahb_0_hrdata(32'b0), + .mmio_ahb_0_hmaster(), + .mmio_ahb_0_hsplit(16'b0), + + .interrupts(2'b0), + + .cdrio_overCLK(clk400), + .cdrio_uDatIn(1'b0), + .cdrio_uDatOut(uDatSer[2]), + .cdrio_dDatIn(dDatSer[2]), + .cdrio_dDatOut() +); + @@ -144,7 +313,6 @@ ExampleRocketSystem s_rocket( - // assign success = debugger_success; @@ -152,8 +320,13 @@ ExampleRocketSystem s_rocket( string testName; -`define MEM s_rocket.ram.Mem_SRAM.Mem_SRAM_ext.ram -reg [7:0] mem [0:200000]; +`define MEM0 s_rocket_mst.ram.Mem_SRAM.Mem_SRAM_ext.ram +`define MEM1 s_rocket_slv0.ram.Mem_SRAM.Mem_SRAM_ext.ram +`define MEM2 s_rocket_slv1.ram.Mem_SRAM.Mem_SRAM_ext.ram +`define MEM3 s_rocket_slv2.ram.Mem_SRAM.Mem_SRAM_ext.ram + +reg [7:0] mem0 [0:200000]; +reg [7:0] mem1 [0:200000]; localparam DP = 8192; integer i; @@ -161,36 +334,40 @@ initial begin #20 - if ( $value$plusargs("%s",testName) ) begin - $display("%s",testName); - $readmemh(testName, mem); - end - else begin - $display("%s",testName); - $error("Failed to read Files!"); - end + // if ( $value$plusargs("%s",testName) ) begin + // $display("%s",testName); + // $readmemh(testName, mem); + // end + // else begin + // $display("%s",testName); + // $error("Failed to read Files!"); + // end - + $readmemh("./tb/sw/build/mstTest.verilog", mem0); for ( i = 0; i < DP; i = i + 1 ) begin - if ( mem[i*4+0] || mem[i*4+1] || mem[i*4+2] || mem[i*4+3] ) begin - `MEM[i] = {mem[i*4+3], mem[i*4+2], mem[i*4+1], mem[i*4+0]}; - - - $display("%x",`MEM[i]); + if ( mem0[i*4+0] || mem0[i*4+1] || mem0[i*4+2] || mem0[i*4+3] ) begin + `MEM0[i] = {mem0[i*4+3], mem0[i*4+2], mem0[i*4+1], mem0[i*4+0]}; end else begin - `MEM[i][7:0] = 8'h0; - `MEM[i][15:8] = 8'h0; - `MEM[i][23:16] = 8'h0; - `MEM[i][31:24] = 8'h0; + `MEM0[i] = 32'h0; end end -end -wire [31:0] test1 = `MEM[0]; -wire [31:0] test2 = `MEM[1]; -wire [31:0] test3 = `MEM[2]; -wire [31:0] test4 = `MEM[3]; + $readmemh("./tb/sw/build/slvTest.verilog", mem1); + for ( i = 0; i < DP; i = i + 1 ) begin + if ( mem1[i*4+0] || mem1[i*4+1] || mem1[i*4+2] || mem1[i*4+3] ) begin + `MEM1[i] = {mem1[i*4+3], mem1[i*4+2], mem1[i*4+1], mem1[i*4+0]}; + `MEM2[i] = {mem1[i*4+3], mem1[i*4+2], mem1[i*4+1], mem1[i*4+0]}; + `MEM3[i] = {mem1[i*4+3], mem1[i*4+2], mem1[i*4+1], mem1[i*4+0]}; + end + else begin + `MEM1[i] = 32'h0; + `MEM2[i] = 32'h0; + `MEM3[i] = 32'h0; + end + end + +end