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重新定向RV编译

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RuigeLee
2025-01-08 09:45:45 +08:00
parent 9d413d70e6
commit 6584c171d5
1 changed files with 5 additions and 5 deletions
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10
Makefile
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@@ -2,13 +2,13 @@
.PHONY: compile tb wave .PHONY: compile tb wave
compile: compile:
rm -rf ./generated/ rm -rf ./generated/Rtpp
rm -rf ./rocket-chip/vsim/generated-src/ rm -rf ./rocket-chip/vsim/generated-src/
mkdir -p ./generated/ mkdir -p ./generated/Rtpp
cd ./rocket-chip/ && rm -f rocketchip.jar cd ./rocket-chip/ && rm -f rocketchip.jar
cd ./rocket-chip/vsim && make verilog CONFIG=freechips.rocketchip.system.UserFPGAConfig cd ./rocket-chip/vsim && make verilog CONFIG=freechips.rocketchip.system.RtppConfig
cp ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.UserFPGAConfig.v ./generated/UserFPGAConfig.v cp ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.RtppConfig.v ./generated/Rtpp/RtppConfig.v
cp ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.UserFPGAConfig.behav_srams.v ./generated/behav_srams.v cp ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.RtppConfig.behav_srams.v ./generated/Rtpp/behav_srams.v
# sbt "test:runMain test.testModule" # sbt "test:runMain test.testModule"
back: back: