From 6584c171d52bc9415fe0c127ce0c4ed2abdb6021 Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Wed, 8 Jan 2025 09:45:45 +0800 Subject: [PATCH] =?UTF-8?q?=E9=87=8D=E6=96=B0=E5=AE=9A=E5=90=91RV=E7=BC=96?= =?UTF-8?q?=E8=AF=91?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Makefile | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/Makefile b/Makefile index e3cd743..9a3264f 100644 --- a/Makefile +++ b/Makefile @@ -2,13 +2,13 @@ .PHONY: compile tb wave compile: - rm -rf ./generated/ + rm -rf ./generated/Rtpp rm -rf ./rocket-chip/vsim/generated-src/ - mkdir -p ./generated/ + mkdir -p ./generated/Rtpp cd ./rocket-chip/ && rm -f rocketchip.jar - cd ./rocket-chip/vsim && make verilog CONFIG=freechips.rocketchip.system.UserFPGAConfig - cp ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.UserFPGAConfig.v ./generated/UserFPGAConfig.v - cp ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.UserFPGAConfig.behav_srams.v ./generated/behav_srams.v + cd ./rocket-chip/vsim && make verilog CONFIG=freechips.rocketchip.system.RtppConfig + cp ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.RtppConfig.v ./generated/Rtpp/RtppConfig.v + cp ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.RtppConfig.behav_srams.v ./generated/Rtpp/behav_srams.v # sbt "test:runMain test.testModule" back: