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软件改完，开始测试

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This commit is contained in:
RuigeLee
2024-11-01 17:07:35 +08:00
parent 08afdee8e3
commit 65491c74f6
5 changed files with 120 additions and 114 deletions
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4
src/main/resources/picorv32.v
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@@ -81,8 +81,8 @@ module picorv32 #(
parameter [ 0:0] REGS_INIT_ZERO = 0,
parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
parameter [31:0] PROGADDR_IRQ = 32'h 0000_0800,
parameter [31:0] PROGADDR_RESET = 32'h 8000_0000,
parameter [31:0] PROGADDR_IRQ = 32'h 8000_0800,
parameter [31:0] STACKADDR = 32'h ffff_ffff
) (
input clk, resetn,

18
src/main/scala/backBoard/pico/BackSystem.scala
View File

@@ -154,24 +154,24 @@ class BackSysImp(outer: BackSys) extends LazyModuleImp(outer) with HasBackParame
sram.io.mem.valid := pico.io.mem.valid & pico.io.mem.addr(13,12) === "b00".U
cdr.io.mem.valid := pico.io.mem.valid & pico.io.mem.addr(13,12) === "b01".U & ~pico.io.mem.instr
gpio.io.mem.valid := pico.io.mem.valid & pico.io.mem.addr(13,12) === "b10".U & ~pico.io.mem.instr
sram.io.mem.valid := pico.io.mem.valid & pico.io.mem.addr.extract(31) === "b1".U
cdr.io.mem.valid := pico.io.mem.valid & pico.io.mem.addr.extract(11) === "b0".U & ~pico.io.mem.instr
gpio.io.mem.valid := pico.io.mem.valid & pico.io.mem.addr.extract(11) === "b1".U & ~pico.io.mem.instr
pico.io.mem.ready :=
Mux( pico.io.mem.instr, sram.io.mem.ready,
Mux1H(Seq(
(pico.io.mem.addr(13,12) === "b00".U ) -> sram.io.mem.ready,
(pico.io.mem.addr(13,12) === "b01".U ) -> cdr.io.mem.ready,
(pico.io.mem.addr(13,12) === "b10".U ) -> gpio.io.mem.ready,
( pico.io.mem.addr.extract(31) === "b1".U ) -> sram.io.mem.ready,
( pico.io.mem.addr.extract(11) === "b0".U ) -> cdr.io.mem.ready,
( pico.io.mem.addr.extract(11) === "b1".U ) -> gpio.io.mem.ready,
))
)
pico.io.mem.rdata :=
Mux( pico.io.mem.instr, sram.io.mem.rdata,
Mux1H(Seq(
(pico.io.mem.addr(13,12) === "b00".U ) -> sram.io.mem.rdata,
(pico.io.mem.addr(13,12) === "b01".U ) -> cdr.io.mem.rdata,
(pico.io.mem.addr(13,12) === "b10".U ) -> gpio.io.mem.rdata,
( pico.io.mem.addr.extract(31) === "b1".U ) -> sram.io.mem.rdata,
( pico.io.mem.addr.extract(11) === "b0".U ) -> cdr.io.mem.rdata,
( pico.io.mem.addr.extract(11) === "b1".U ) -> gpio.io.mem.rdata,
))
)