tl to axi in single device

src/main/scala/mac/MAC.scala

@@ -14,7 +14,7 @@ class Mac(implicit p: Parameters) extends LazyModule with HasMacParameters{
   val tlMasterNode =   
         TLManagerNode(Seq(TLSlavePortParameters.v1(
           managers = Seq(TLSlaveParameters.v1(
-          address = Seq(AddressSet(0x00000000L, 0x0FFFL)),
+          address = Seq(AddressSet(0x30000000L, 0x0FFFL)),
           regionType = RegionType.UNCACHED,
           executable = false,
           supportsGet         = TransferSizes(32/8, 32/8),

src/main/scala/mac/Rocket/RocketMac.scala

@@ -0,0 +1,35 @@
+// package Top
+
+// import chisel3._
+// import Mac._
+
+
+// import freechips.rocketchip.system._
+// import org.chipsalliance.cde.config.Parameters
+// import freechips.rocketchip.subsystem._
+// import freechips.rocketchip.devices.tilelink._
+// import freechips.rocketchip.util.DontTouch
+
+
+
+// /** Example Top with periphery devices and ports, and a Rocket subsystem */
+// class ExampleRocketSystem(implicit p: Parameters) extends RocketSubsystem
+//     with HasAsyncExtInterrupts
+//     with CanHaveMasterAXI4MemPort
+//     with CanHaveMasterAXI4MMIOPort
+//     with CanHaveSlaveAXI4Port
+//     with WithManyMacMix
+// {
+//   // optionally add ROM devices
+//   // Note that setting BootROMLocated will override the reset_vector for all tiles
+//   val bootROM  = p(BootROMLocated(location)).map { BootROM.attach(_, this, CBUS) }
+//   val maskROMs = p(MaskROMLocated(location)).map { MaskROM.attach(_, this, CBUS) }
+
+//   override lazy val module = new ExampleRocketSystemModuleImp(this)
+// }
+
+// class ExampleRocketSystemModuleImp[+L <: ExampleRocketSystem](_outer: L) extends RocketSubsystemModuleImp(_outer)
+//     with HasRTCModuleImp
+//     with HasExtInterruptsModuleImp
+//     with DontTouch
+

src/main/scala/mac/WithMac.scala

@@ -12,7 +12,7 @@ trait WithManyMacMix { this: BaseSubsystem =>
     val mac = LazyModule(new Mac)
 
     fbus.coupleFrom("mac_mst") { _ := TLBuffer() := mac.tlClientNode }
-    pbus.coupleTo("mac_cfg") { mac.tlMasterNode := TLFragmenter(4, pbus.blockBytes) := TLWidthWidget(pbus.beatBytes) := _ }
+    pbus.coupleTo("mac_cfg")   { mac.tlMasterNode := _ } //TLFragmenter(4, pbus.blockBytes) := TLWidthWidget(pbus.beatBytes) := 
 
     ibus.fromSync := mac.int_node